igb: add support for reporting 5GT/s during probe on PCIe Gen2

This change corrects the fact that we were not reporting Gen2 link speeds
when we were in fact connected at Gen2 rates.

Signed-off-by: Alexander Duyck <alexander.h.duyck@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
Signed-off-by: David S. Miller <davem@davemloft.net>

diff --git a/drivers/net/igb/e1000_defines.h b/drivers/net/igb/e1000_defines.h
index 31d24e0e76deb8915cad793d14c78d57be96fea5..24d9be64342ff91d75119c149618194a9e1485ae 100644 (file)
--- a/drivers/net/igb/e1000_defines.h
+++ b/drivers/net/igb/e1000_defines.h
@@ -610,11 +610,7 @@
 #define IGP_LED3_MODE           0x07000000
 
 /* PCI/PCI-X/PCI-EX Config space */
-#define PCIE_LINK_STATUS             0x12
 #define PCIE_DEVICE_CONTROL2         0x28
-
-#define PCIE_LINK_WIDTH_MASK         0x3F0
-#define PCIE_LINK_WIDTH_SHIFT        4
 #define PCIE_DEVICE_CONTROL2_16ms    0x0005
 
 #define PHY_REVISION_MASK      0xFFFFFFF0

diff --git a/drivers/net/igb/e1000_mac.c b/drivers/net/igb/e1000_mac.c
index be8d010e40213a7b51616fad0e320464a43c751a..90c5e01e9235875ba6b954e31ab3a52cbcee9fb1 100644 (file)
--- a/drivers/net/igb/e1000_mac.c
+++ b/drivers/net/igb/e1000_mac.c
@@ -53,17 +53,30 @@ s32 igb_get_bus_info_pcie(struct e1000_hw *hw)
        u16 pcie_link_status;
 
        bus->type = e1000_bus_type_pci_express;
-       bus->speed = e1000_bus_speed_2500;
 
        ret_val = igb_read_pcie_cap_reg(hw,
-                                         PCIE_LINK_STATUS,
-                                         &pcie_link_status);
-       if (ret_val)
+                                       PCI_EXP_LNKSTA,
+                                       &pcie_link_status);
+       if (ret_val) {
                bus->width = e1000_bus_width_unknown;
-       else
+               bus->speed = e1000_bus_speed_unknown;
+       } else {
+               switch (pcie_link_status & PCI_EXP_LNKSTA_CLS) {
+               case PCI_EXP_LNKSTA_CLS_2_5GB:
+                       bus->speed = e1000_bus_speed_2500;
+                       break;
+               case PCI_EXP_LNKSTA_CLS_5_0GB:
+                       bus->speed = e1000_bus_speed_5000;
+                       break;
+               default:
+                       bus->speed = e1000_bus_speed_unknown;
+                       break;
+               }
+
                bus->width = (enum e1000_bus_width)((pcie_link_status &
-                                                    PCIE_LINK_WIDTH_MASK) >>
-                                                    PCIE_LINK_WIDTH_SHIFT);
+                                                    PCI_EXP_LNKSTA_NLW) >>
+                                                    PCI_EXP_LNKSTA_NLW_SHIFT);
+       }
 
        reg = rd32(E1000_STATUS);
        bus->func = (reg & E1000_STATUS_FUNC_MASK) >> E1000_STATUS_FUNC_SHIFT;

diff --git a/drivers/net/igb/igb_main.c b/drivers/net/igb/igb_main.c
index a14303a0ad7b9fcfccab2e6cc057e92bb8879ab8..919e36386675feb8f2a4cad855d35a9d8eba3415 100644 (file)
--- a/drivers/net/igb/igb_main.c
+++ b/drivers/net/igb/igb_main.c
@@ -1638,6 +1638,7 @@ static int __devinit igb_probe(struct pci_dev *pdev,
        dev_info(&pdev->dev, "%s: (PCIe:%s:%s) %pM\n",
                 netdev->name,
                 ((hw->bus.speed == e1000_bus_speed_2500) ? "2.5Gb/s" :
+                 (hw->bus.speed == e1000_bus_speed_5000) ? "5.0Gb/s" :
                                                            "unknown"),
                 ((hw->bus.width == e1000_bus_width_pcie_x4) ? "Width x4" :
                  (hw->bus.width == e1000_bus_width_pcie_x2) ? "Width x2" :

diff --git a/include/linux/pci_regs.h b/include/linux/pci_regs.h
index c8f302991b669c37ff8226b60f0b2307703c86f9..c4c3d68be19ad150561d9e885bd35cb0d0825993 100644 (file)
--- a/include/linux/pci_regs.h
+++ b/include/linux/pci_regs.h
@@ -442,7 +442,10 @@
 #define  PCI_EXP_LNKCTL_LABIE  0x0800  /* Lnk Autonomous Bandwidth Interrupt Enable */
 #define PCI_EXP_LNKSTA         18      /* Link Status */
 #define  PCI_EXP_LNKSTA_CLS    0x000f  /* Current Link Speed */
+#define  PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
+#define  PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
 #define  PCI_EXP_LNKSTA_NLW    0x03f0  /* Nogotiated Link Width */
+#define  PCI_EXP_LNKSTA_NLW_SHIFT 4    /* start of NLW mask in link status */
 #define  PCI_EXP_LNKSTA_LT     0x0800  /* Link Training */
 #define  PCI_EXP_LNKSTA_SLC    0x1000  /* Slot Clock Configuration */
 #define  PCI_EXP_LNKSTA_DLLLA  0x2000  /* Data Link Layer Link Active */