static DEFINE_SPINLOCK(irq_controller_lock);
+/* Address of GIC 0 CPU interface */
+void __iomem *gic_cpu_base_addr;
+
struct gic_chip_data {
unsigned int irq_offset;
void __iomem *dist_base;
void __init gic_init(unsigned int gic_nr, unsigned int irq_start,
void __iomem *dist_base, void __iomem *cpu_base)
{
+ if (gic_nr == 0)
+ gic_cpu_base_addr = cpu_base;
gic_dist_init(gic_nr, dist_base, irq_start);
gic_cpu_init(gic_nr, cpu_base);
}
#define GIC_DIST_SOFTINT 0xf00
#ifndef __ASSEMBLY__
+extern void __iomem *gic_cpu_base_addr;
+
void gic_init(unsigned int, unsigned int, void __iomem *, void __iomem *);
void gic_secondary_init(unsigned int);
void gic_cascade_irq(unsigned int gic_nr, unsigned int irq);
}
/* used by entry-macro.S */
-void __iomem *gic_cpu_base_addr;
-
void __init cns3xxx_init_irq(void)
{
- gic_cpu_base_addr = __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT);
gic_init(0, 29, __io(CNS3XXX_TC11MP_GIC_DIST_BASE_VIRT),
- gic_cpu_base_addr);
+ __io(CNS3XXX_TC11MP_GIC_CPU_BASE_VIRT));
}
void cns3xxx_power_off(void)
#ifndef __CNS3XXX_CORE_H
#define __CNS3XXX_CORE_H
-extern void __iomem *gic_cpu_base_addr;
extern struct sys_timer cns3xxx_timer;
void __init cns3xxx_map_io(void);
#include <mach/board.h>
#include <mach/msm_iomap.h>
-void __iomem *gic_cpu_base_addr;
-
unsigned long clk_get_max_axi_khz(void)
{
return 0;
{
unsigned int i;
- gic_cpu_base_addr = (void *)MSM_QGIC_CPU_BASE;
- gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE, gic_cpu_base_addr);
+ gic_init(0, GIC_PPI_START, MSM_QGIC_DIST_BASE,
+ (void *)MSM_QGIC_CPU_BASE);
/* Edge trigger PPIs except AVS_SVICINT and AVS_SVICINTSWDONE */
writel(0xFFFFD7FF, MSM_QGIC_DIST_BASE + GIC_DIST_CONFIG + 4);
extern void __iomem *l2cache_base;
#endif
-extern void __iomem *gic_cpu_base_addr;
extern void __iomem *gic_dist_base_addr;
extern void __init gic_init_irq(void);
void __iomem *l2cache_base;
#endif
-void __iomem *gic_cpu_base_addr;
void __iomem *gic_dist_base_addr;
void __init gic_init_irq(void)
{
+ void __iomem *gic_cpu_base;
+
/* Static mapping, never released */
gic_dist_base_addr = ioremap(OMAP44XX_GIC_DIST_BASE, SZ_4K);
BUG_ON(!gic_dist_base_addr);
/* Static mapping, never released */
- gic_cpu_base_addr = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
- BUG_ON(!gic_cpu_base_addr);
+ gic_cpu_base = ioremap(OMAP44XX_GIC_CPU_BASE, SZ_512);
+ BUG_ON(!gic_cpu_base);
- gic_init(0, 29, gic_dist_base_addr, gic_cpu_base_addr);
+ gic_init(0, 29, gic_dist_base_addr, gic_cpu_base);
}
#ifdef CONFIG_CACHE_L2X0
#include "core.h"
-/* used by entry-macro.S and platsmp.c */
-void __iomem *gic_cpu_base_addr;
-
#ifdef CONFIG_ZONE_DMA
/*
* Adjust the zones if there are restrictions for DMA access.
extern struct mmci_platform_data realview_mmc0_plat_data;
extern struct mmci_platform_data realview_mmc1_plat_data;
extern struct clcd_board clcd_plat_data;
-extern void __iomem *gic_cpu_base_addr;
extern void __iomem *timer0_va_base;
extern void __iomem *timer1_va_base;
extern void __iomem *timer2_va_base;
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
/* core tile GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_EB11MP_GIC_CPU_BASE);
gic_init(0, 29, __io_address(REALVIEW_EB11MP_GIC_DIST_BASE),
- gic_cpu_base_addr);
+ __io_address(REALVIEW_EB11MP_GIC_CPU_BASE));
#ifndef CONFIG_REALVIEW_EB_ARM11MP_REVB
/* board GIC, secondary */
#endif
} else {
/* board GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_EB_GIC_CPU_BASE);
gic_init(0, 29, __io_address(REALVIEW_EB_GIC_DIST_BASE),
- gic_cpu_base_addr);
+ __io_address(REALVIEW_EB_GIC_CPU_BASE));
}
}
static void __init gic_init_irq(void)
{
/* ARM1176 DevChip GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_DC1176_GIC_CPU_BASE);
gic_init(0, IRQ_DC1176_GIC_START,
__io_address(REALVIEW_DC1176_GIC_DIST_BASE),
- gic_cpu_base_addr);
+ __io_address(REALVIEW_DC1176_GIC_CPU_BASE));
/* board GIC, secondary */
gic_init(1, IRQ_PB1176_GIC_START,
writel(0x00000000, __io_address(REALVIEW_SYS_LOCK));
/* ARM11MPCore test chip GIC, primary */
- gic_cpu_base_addr = __io_address(REALVIEW_TC11MP_GIC_CPU_BASE);
gic_init(0, 29, __io_address(REALVIEW_TC11MP_GIC_DIST_BASE),
- gic_cpu_base_addr);
+ __io_address(REALVIEW_TC11MP_GIC_CPU_BASE));
/* board GIC, secondary */
gic_init(1, IRQ_PB11MP_GIC_START,
static void __init gic_init_irq(void)
{
/* ARM PB-A8 on-board GIC */
- gic_cpu_base_addr = __io_address(REALVIEW_PBA8_GIC_CPU_BASE);
gic_init(0, IRQ_PBA8_GIC_START,
__io_address(REALVIEW_PBA8_GIC_DIST_BASE),
__io_address(REALVIEW_PBA8_GIC_CPU_BASE));
{
/* ARM PBX on-board GIC */
if (core_tile_pbx11mp() || core_tile_pbxa9mp()) {
- gic_cpu_base_addr = __io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE);
gic_init(0, 29, __io_address(REALVIEW_PBX_TILE_GIC_DIST_BASE),
__io_address(REALVIEW_PBX_TILE_GIC_CPU_BASE));
} else {
- gic_cpu_base_addr = __io_address(REALVIEW_PBX_GIC_CPU_BASE);
gic_init(0, IRQ_PBX_GIC_START,
__io_address(REALVIEW_PBX_GIC_DIST_BASE),
__io_address(REALVIEW_PBX_GIC_CPU_BASE));
#include <mach/regs-irq.h>
-void __iomem *gic_cpu_base_addr;
-
extern int combiner_init(unsigned int combiner_nr, void __iomem *base,
unsigned int irq_start);
extern void combiner_cascade_irq(unsigned int combiner_nr, unsigned int irq);
{
int irq;
- gic_cpu_base_addr = S5P_VA_GIC_CPU;
gic_init(0, IRQ_LOCALTIMER, S5P_VA_GIC_DIST, S5P_VA_GIC_CPU);
for (irq = 0; irq < MAX_COMBINER_NR; irq++) {
#include <asm/hardware/gic.h>
#include <asm/smp_mpidr.h>
-extern void __iomem *gic_cpu_base_addr;
-
/*
* We use IRQ1 as the IPI
*/
void v2m_map_io(struct map_desc *tile, size_t num);
extern struct sys_timer v2m_timer;
-
-extern void __iomem *gic_cpu_base_addr;
v2m_map_io(ct_ca9x4_io_desc, ARRAY_SIZE(ct_ca9x4_io_desc));
}
-void __iomem *gic_cpu_base_addr;
-
static void __init ct_ca9x4_init_irq(void)
{
- gic_cpu_base_addr = MMIO_P2V(A9_MPCORE_GIC_CPU);
- gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST), gic_cpu_base_addr);
+ gic_init(0, 29, MMIO_P2V(A9_MPCORE_GIC_DIST),
+ MMIO_P2V(A9_MPCORE_GIC_CPU));
}
#if 0