#define SPI_BUS 6 /* gSPI target */
#define RPC_BUS 7 /* RPC target */
-#define CHIPREV(rev) (rev)
/* Defines for DMA Address Width - Shared between OSL and HNDDMA */
#define DMADDR_MASK_32 0x0 /* Address mask for 32-bits */
printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
__func__, wlc_hw->sih->chip,
- CHIPREV(wlc_hw->sih->chiprev));
+ wlc_hw->sih->chiprev);
WLCNTINCR(wlc->pub->_cnt->psmwds);
printk_once("%s : PSM Watchdog, chipid 0x%x, chiprev 0x%x\n",
__func__, wlc->pub->sih->chip,
- CHIPREV(wlc->pub->sih->chiprev));
+ wlc->pub->sih->chiprev);
WLCNTINCR(wlc->pub->_cnt->psmwds);
#include <bcmdevs.h>
#define BCM47162_DMP() ((sih->chip == BCM47162_CHIP_ID) && \
- (CHIPREV(sih->chiprev) == 0) && \
+ (sih->chiprev == 0) && \
(sii->coreid[sii->curidx] == MIPS74K_CORE_ID))
/* EROM parsing */
si_pmu_set_4330_plldivs(sih);
if ((sih->chip == BCM4329_CHIP_ID)
- && (CHIPREV(sih->chiprev) == 0)) {
+ && (sih->chiprev == 0)) {
W_REG(osh, &cc->pllcontrol_addr, PMU1_PLL0_PLLCTL1);
tmp = R_REG(osh, &cc->pllcontrol_data);
((xt->xf << PCTL_XTALFREQ_SHIFT) & PCTL_XTALFREQ_MASK);
if ((sih->chip == BCM4329_CHIP_ID)
- && CHIPREV(sih->chiprev) == 0) {
+ && sih->chiprev == 0) {
/* clear the htstretch before clearing HTReqEn */
AND_REG(osh, &cc->clkstretch, ~CSTRETCH_HT);
tmp &= ~PCTL_HT_REQ_EN;
PMU5_MAINPLL_SI);
break;
case BCM4329_CHIP_ID:
- if (CHIPREV(sih->chiprev) == 0)
+ if (sih->chiprev == 0)
clock = 38400 * 1000;
else
clock = si_pmu1_cpuclk0(sih, osh, cc);
0xe);
/* Reduce LNLDO1 output voltage to 1.2V */
si_pmu_set_ldo_voltage(sih, osh, SET_LDO_VOLTAGE_LNLDO1, 0xe);
- if (CHIPREV(sih->chiprev) == 0)
+ if (sih->chiprev == 0)
si_pmu_regcontrol(sih, 2, 0x400000, 0x400000);
break;
((sih->chip == BCM43236_CHIP_ID
|| sih->chip == BCM43235_CHIP_ID
|| sih->chip == BCM43238_CHIP_ID)
- && (CHIPREV(sii->pub.chiprev) <= 2))) {
+ && (sii->pub.chiprev <= 2))) {
if ((cc->chipstatus & CST43236_BP_CLK) != 0) {
uint clkdiv;
if ((sih->chip == BCM43224_CHIP_ID) ||
(sih->chip == BCM43421_CHIP_ID)) {
/* enable 12 mA drive strenth for 43224 and set chipControl register bit 15 */
- if (CHIPREV(sih->chiprev) == 0) {
+ if (sih->chiprev == 0) {
SI_MSG(("Applying 43224A0 WARs\n"));
si_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, chipcontrol),
si_pmu_chipcontrol(sih, 0, CCTRL_43224A0_12MA_LED_DRIVE,
CCTRL_43224A0_12MA_LED_DRIVE);
}
- if (CHIPREV(sih->chiprev) >= 1) {
+ if (sih->chiprev >= 1) {
SI_MSG(("Applying 43224B0+ WARs\n"));
si_pmu_chipcontrol(sih, 0, CCTRL_43224B0_12MA_LED_DRIVE,
CCTRL_43224B0_12MA_LED_DRIVE);
if (PMUCTL_ENAB(sih)) {
if ((sih->chip == BCM4319_CHIP_ID) &&
- (CHIPREV(sih->chiprev) == 0) && (ticks != 0)) {
+ (sih->chiprev == 0) && (ticks != 0)) {
si_corereg(sih, SI_CC_IDX,
offsetof(chipcregs_t, clk_ctl_st), ~0, 0x2);
si_setcore(sih, USB20D_CORE_ID, 0);