i40iw: Fix sequence number for the first partial FPDU
authorShiraz Saleem <shiraz.saleem@intel.com>
Fri, 22 Dec 2017 15:46:59 +0000 (09:46 -0600)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Fri, 13 Apr 2018 17:48:08 +0000 (19:48 +0200)
[ Upstream commit df8b13a1b23356d01dfc4647a5629cdb0f4ce566 ]

Partial FPDU processing is broken as the sequence number
for the first partial FPDU is wrong due to incorrect
Q2 buffer offset. The offset should be 64 rather than 16.

Fixes: 786c6adb3a94 ("i40iw: add puda code")
Signed-off-by: Shiraz Saleem <shiraz.saleem@intel.com>
Signed-off-by: Jason Gunthorpe <jgg@mellanox.com>
Signed-off-by: Sasha Levin <alexander.levin@microsoft.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
drivers/infiniband/hw/i40iw/i40iw_d.h
drivers/infiniband/hw/i40iw/i40iw_puda.c

index d1328a6977509cc3cc689a7cc83d329c7c232f91..8ce599e1639c35644aa6129a02ebb625fb0fb6a8 100644 (file)
@@ -86,6 +86,7 @@
 #define RDMA_OPCODE_MASK        0x0f
 #define RDMA_READ_REQ_OPCODE    1
 #define Q2_BAD_FRAME_OFFSET     72
+#define Q2_FPSN_OFFSET          64
 #define CQE_MAJOR_DRV           0x8000
 
 #define I40IW_TERM_SENT 0x01
index c62d354f78102c6e31ff8b65aae4a1be9c021948..3ed49146d73c0423f5159cda37fe362e9ae8eb15 100644 (file)
@@ -1320,7 +1320,7 @@ static void i40iw_ieq_handle_exception(struct i40iw_puda_rsrc *ieq,
        u32 *hw_host_ctx = (u32 *)qp->hw_host_ctx;
        u32 rcv_wnd = hw_host_ctx[23];
        /* first partial seq # in q2 */
-       u32 fps = qp->q2_buf[16];
+       u32 fps = *(u32 *)(qp->q2_buf + Q2_FPSN_OFFSET);
        struct list_head *rxlist = &pfpdu->rxlist;
        struct list_head *plist;