x86: nmi: Add Intel processor 0x6f4 to NMI perfctr1 workaround
authorPrarit Bhargava <prarit@redhat.com>
Wed, 10 Jun 2009 19:41:02 +0000 (12:41 -0700)
committerIngo Molnar <mingo@elte.hu>
Wed, 17 Jun 2009 16:20:39 +0000 (18:20 +0200)
Expand Intel NMI perfctr1 workaround to include a Core2 processor stepping
(cpuid family-6, model-f, stepping-4).  Resolves a situation where the NMI
would not enable on these processors.

Signed-off-by: Prarit Bhargava <prarit@redhat.com>
Acked-by: Suresh Siddha <suresh.b.siddha@intel.com>
Cc: prarit@redhat.com
Cc: suresh.b.siddha@intel.com
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Ingo Molnar <mingo@elte.hu>
arch/x86/kernel/cpu/perfctr-watchdog.c

index d6f5b9fbde3253a2a8405dfaa1070184e8288d72..5c481f6205bfc3f591d32f3ef4b4cd850ba2d37a 100644 (file)
@@ -716,11 +716,15 @@ static void probe_nmi_watchdog(void)
                wd_ops = &k7_wd_ops;
                break;
        case X86_VENDOR_INTEL:
-               /*
-                * Work around Core Duo (Yonah) errata AE49 where perfctr1
-                * doesn't have a working enable bit.
+               /* Work around where perfctr1 doesn't have a working enable
+                * bit as described in the following errata:
+                * AE49 Core Duo and Intel Core Solo 65 nm
+                * AN49 Intel Pentium Dual-Core
+                * AF49 Dual-Core Intel Xeon Processor LV
                 */
-               if (boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) {
+               if ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 14) ||
+                   ((boot_cpu_data.x86 == 6 && boot_cpu_data.x86_model == 15 &&
+                    boot_cpu_data.x86_mask == 4))) {
                        intel_arch_wd_ops.perfctr = MSR_ARCH_PERFMON_PERFCTR0;
                        intel_arch_wd_ops.evntsel = MSR_ARCH_PERFMON_EVENTSEL0;
                }