PD#126286 rm max pp and min pp for midgard
authorJiyu Yang <jiyu.yang@amlogic.com>
Tue, 7 Jun 2016 06:47:30 +0000 (14:47 +0800)
committerSimon Zheng <simon.zheng@amlogic.com>
Mon, 27 Jun 2016 12:44:40 +0000 (05:44 -0700)
Change-Id: Idfb467f2172a54aa65133c858a2717d4ff111749

t83x/kernel/drivers/gpu/arm/midgard/platform/devicetree/mpgpu.c

index 4c5e26fa11bb164f7b1cb61e2925563847be63d8..0cc5035ab766df0dedc2882de10d867890db63f9 100644 (file)
@@ -135,6 +135,7 @@ static ssize_t scale_mode_write(struct class *class,
        return count;
 }
 
+#if 0
 static ssize_t max_pp_read(struct class *class,
                struct class_attribute *attr, char *buf)
 {
@@ -194,6 +195,7 @@ static ssize_t min_pp_write(struct class *class,
 
        return count;
 }
+#endif
 
 static ssize_t max_freq_read(struct class *class,
                struct class_attribute *attr, char *buf)
@@ -277,6 +279,7 @@ static ssize_t freq_write(struct class *class,
        return count;
 }
 
+#if 0
 static ssize_t current_pp_read(struct class *class,
                struct class_attribute *attr, char *buf)
 {
@@ -307,6 +310,7 @@ static ssize_t current_pp_write(struct class *class,
 
        return count;
 }
+#endif
 
 static struct class_attribute mali_class_attrs[] = {
        __ATTR(domain_stat,     0644, domain_stat_read, NULL),
@@ -314,10 +318,14 @@ static struct class_attribute mali_class_attrs[] = {
        __ATTR(scale_mode,      0644, scale_mode_read,  scale_mode_write),
        __ATTR(min_freq,        0644, min_freq_read,    min_freq_write),
        __ATTR(max_freq,        0644, max_freq_read,    max_freq_write),
+#if 0
        __ATTR(min_pp,          0644, min_pp_read,      min_pp_write),
        __ATTR(max_pp,          0644, max_pp_read,      max_pp_write),
+#endif
        __ATTR(cur_freq,        0644, freq_read,        freq_write),
+#if 0
        __ATTR(cur_pp,          0644, current_pp_read,  current_pp_write),
+#endif
 };
 
 static struct class mpgpu_class = {