arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC

Commit 7175f0591eb9 ("arm64: perf: Enable PMCR long cycle counter bit")
added initial support for a 64-bit cycle counter enabled using PMCR.LC.

Unfortunately, that patch doesn't extend ARMV8_EVTYPE_MASK, so any
attempts to set the enable bit are ignored by armv8pmu_pmcr_write.

This patch extends the mask to include the new bit.

Signed-off-by: Will Deacon <will.deacon@arm.com>

diff --git a/arch/arm64/kernel/perf_event.c b/arch/arm64/kernel/perf_event.c
index 1cc61fc321d99ad02c219b5a1e9c7bbb6a9e05cf..c4c97655662e7f75a42bfef505299c2a7a223053 100644 (file)
--- a/arch/arm64/kernel/perf_event.c
+++ b/arch/arm64/kernel/perf_event.c
@@ -408,7 +408,7 @@ static const struct attribute_group *armv8_pmuv3_attr_groups[] = {
 #define ARMV8_PMCR_LC          (1 << 6) /* Overflow on 64 bit cycle counter */
 #define        ARMV8_PMCR_N_SHIFT      11       /* Number of counters supported */
 #define        ARMV8_PMCR_N_MASK       0x1f
-#define        ARMV8_PMCR_MASK         0x3f     /* Mask for writable bits */
+#define        ARMV8_PMCR_MASK         0x7f     /* Mask for writable bits */
 
 /*
  * PMOVSR: counters overflow flag status reg