static int xilinx_download(struct comedi_device *dev)
{
+ struct pci_dev *pcidev = comedi_to_pci_dev(dev);
struct me4000_info *info = dev->private;
+ unsigned long xilinx_iobase = pci_resource_start(pcidev, 5);
u32 value = 0;
wait_queue_head_t queue;
int idx = 0;
int size = 0;
+ if (!xilinx_iobase)
+ return -ENODEV;
+
init_waitqueue_head(&queue);
/*
outl(value, info->plx_regbase + PLX_ICR);
/* Init Xilinx with CS1 */
- inb(info->program_regbase + 0xC8);
+ inb(xilinx_iobase + 0xC8);
/* Wait until /INIT pin is set */
udelay(20);
udelay(10);
for (idx = 0; idx < size; idx++) {
- outb(xilinx_firm[16 + idx], info->program_regbase);
+ outb(xilinx_firm[16 + idx], xilinx_iobase);
udelay(10);
/* Check if BUSY flag is low */
if (!info->timer_regbase)
return -ENODEV;
- info->program_regbase = pci_resource_start(pcidev, 5);
- if (!info->program_regbase)
- return -ENODEV;
-
dev->irq = pcidev->irq;
result = xilinx_download(dev);
struct me4000_info {
unsigned long plx_regbase; /* PLX configuration space base address */
unsigned long timer_regbase; /* Base address of the timer circuit */
- unsigned long program_regbase; /* Base address to set the program pin for the xilinx */
unsigned int ao_readback[4];
};