{"PAFSTAT_CORE1_IN_CSIS0_EN", 0, 1, RW, 0x1},
};
-#define MUX_SET_VAL_DEFAULT (0x00172077)
+/*
+ * [22:21] GLUEMUX_PAF_DMA3_OTF_SEL[1:0] : 0 = DMA0, 1 = DMA1, 2 = DMA2, 3 = DMA3
+ * [20:19] GLUEMUX_PAF_DMA2_OTF_SEL[1:0] : 0 = DMA0, 1 = DMA1, 2 = DMA2, 3 = DMA3
+ * [18:17] GLUEMUX_PAF_DMA1_OTF_SEL[1:0] : 0 = DMA0, 1 = DMA1, 2 = DMA2, 3 = DMA3
+ * [16:15] GLUEMUX_PAF_DMA0_OTF_SEL[1:0] : 0 = DMA0, 1 = DMA1, 2 = DMA2, 3 = DMA3
+ * [14:13] MUX_3AA1_VAL[1:0] : 0 = CSIS0, 1 = CSIS1, 2 = CSIS2, 3 = CSIS3
+ * [12:11] MUX_3AA0_VAL[1:0] : 0 = CSIS0, 1 = CSIS1, 2 = CSIS2, 3 = CSIS3
+ * [10] CSIS2_DPHY_S_MUXSEL : 0 : S4(2) of M4S4S4, 1: S4(2) of M2S4S4S2
+ * [9] CSIS1_DPHY_S_MUXSEL : 0 : S4(2) of M4S4S4, 1: S4(2) of M2S4S4S2
+ * [8] CSIS0_DPHY_S_MUXSEL : 0 : S4(2) of M4S4S4, 1: S4(2) of M2S4S4S2
+ * [7] I_PAFSTAT_CORE1_IN_CSIS3_EN
+ * [6] I_PAFSTAT_CORE1_IN_CSIS2_EN
+ * [5] I_PAFSTAT_CORE1_IN_CSIS1_EN
+ * [4] I_PAFSTAT_CORE1_IN_CSIS0_EN
+ * [3] I_PAFSTAT_CORE0_IN_CSIS3_EN
+ * [2] I_PAFSTAT_CORE0_IN_CSIS2_EN
+ * [1] I_PAFSTAT_CORE0_IN_CSIS1_EN
+ * [0] I_PAFSTAT_CORE0_IN_CSIS0_EN
+ */
+#define MUX_SET_VAL_DEFAULT (0x00402077)
#define MUX_CLR_VAL_DEFAULT (0x007FFFFF)
/* Define default subdev ops if there are not used subdev IP */