drm/i915: treat Ivy Bridge watermarks like Sandy Bridge

Not fully tested.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>

diff --git a/drivers/gpu/drm/i915/intel_display.c b/drivers/gpu/drm/i915/intel_display.c
index 5ccd18f62e43d2d962b0e48fcd224f47107b1c03..b1de6cb7480350a0c39e3a4c93278011cfb368b2 100644 (file)
--- a/drivers/gpu/drm/i915/intel_display.c
+++ b/drivers/gpu/drm/i915/intel_display.c
@@ -7298,7 +7298,7 @@ void intel_enable_clock_gating(struct drm_device *dev)
                                   _3D_CHICKEN2_WM_READ_PIPELINED);
                }
 
-               if (IS_GEN6(dev)) {
+               if (IS_GEN6(dev) || IS_IVYBRIDGE(dev)) {
                        I915_WRITE(WM3_LP_ILK, 0);
                        I915_WRITE(WM2_LP_ILK, 0);
                        I915_WRITE(WM1_LP_ILK, 0);
@@ -7560,6 +7560,13 @@ static void intel_init_display(struct drm_device *dev)
                } else if (IS_IVYBRIDGE(dev)) {
                        /* FIXME: detect B0+ stepping and use auto training */
                        dev_priv->display.fdi_link_train = ivb_manual_fdi_link_train;
+                       if (SNB_READ_WM0_LATENCY()) {
+                               dev_priv->display.update_wm = sandybridge_update_wm;
+                       } else {
+                               DRM_DEBUG_KMS("Failed to read display plane latency. "
+                                             "Disable CxSR\n");
+                               dev_priv->display.update_wm = NULL;
+                       }
                } else
                        dev_priv->display.update_wm = NULL;
        } else if (IS_PINEVIEW(dev)) {