i++, index += cpu_data->icache.way_incr)
ctrl_outl(0, index); /* Clear out Valid-bit */
back_to_P1();
+ wmb();
local_irq_restore(flags);
}
flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x2000, phys);
flush_cache_4096(CACHE_OC_ADDRESS_ARRAY | 0x3000, phys);
}
+
+ wmb();
}
static inline void flush_icache_all(void)
__flush_dcache_all();
else
__flush_dcache_all_ex();
+ wmb();
}
void flush_cache_all(void)
struct page *page, unsigned long addr, int len)
{
flush_cache_page(vma, addr, page_to_pfn(page));
+ mb();
}
extern void __xchg_called_with_bad_pointer(void);
+#ifdef CONFIG_CPU_SH4A
+#define mb() __asm__ __volatile__ ("synco": : :"memory")
+#define rmb() mb()
+#define wmb() __asm__ __volatile__ ("synco": : :"memory")
+#define read_barrier_depends() do { } while(0)
+#else
#define mb() __asm__ __volatile__ ("": : :"memory")
#define rmb() mb()
#define wmb() __asm__ __volatile__ ("": : :"memory")
#define read_barrier_depends() do { } while(0)
+#endif
#ifdef CONFIG_SMP
#define smp_mb() mb()