[9610] gpu: tHEx: r10p0: update definition for pm-qos cpu

Change-Id: Ib2c74c4f857c7b4db615928b66f274a850f38fbf
Signed-off-by: Jinku Kang <jinku79.kang@samsung.com>

diff --git a/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_exynos9610.c b/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_exynos9610.c
index 41cc822c9b65bebc62b081051954a9a184908c5e..f57cac282b864458cb7523f34fb551d7f385d8da 100644 (file)
--- a/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_exynos9610.c
+++ b/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_exynos9610.c
@@ -52,7 +52,7 @@ extern int s2m_get_dvs_is_on(void);
 #define LOCAL_PWR_CFG                          (0xF << 0)
 
 #ifdef CONFIG_MALI_DVFS
-#define CPU_MAX PM_QOS_CLUSTER1_FREQ_MAX_DEFAULT_VALUE
+#define CPU_MAX PM_QOS_CPU_FREQ_MAX_DEFAULT_VALUE
 #else
 #define CPU_MAX -1
 #endif

diff --git a/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_pmqos.c b/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_pmqos.c
index febb2d3bd7942622f941522bfaa7f3be00935170..80b6b4b3bcb9a483b3e6875292252d22e5b48b43 100644 (file)
--- a/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_pmqos.c
+++ b/drivers/gpu/arm/tHEx/r10p0/platform/exynos/gpu_pmqos.c
@@ -53,7 +53,7 @@ int gpu_pm_qos_command(struct exynos_context *platform, gpu_pmqos_state state)
                if (!platform->pmqos_int_disable)
                        pm_qos_add_request(&exynos5_g3d_int_qos, PM_QOS_DEVICE_THROUGHPUT, 0);
                pm_qos_add_request(&exynos5_g3d_cpu_cluster0_min_qos, PM_QOS_CLUSTER0_FREQ_MIN, 0);
-               pm_qos_add_request(&exynos5_g3d_cpu_cluster1_max_qos, PM_QOS_CLUSTER1_FREQ_MAX, PM_QOS_CLUSTER1_FREQ_MAX_DEFAULT_VALUE);
+               pm_qos_add_request(&exynos5_g3d_cpu_cluster1_max_qos, PM_QOS_CLUSTER1_FREQ_MAX, PM_QOS_CPU_FREQ_MAX_DEFAULT_VALUE);
                if (platform->boost_egl_min_lock)
                        pm_qos_add_request(&exynos5_g3d_cpu_cluster1_min_qos, PM_QOS_CLUSTER1_FREQ_MIN, 0);
                for (idx = 0; idx < platform->table_size; idx++)
@@ -110,7 +110,7 @@ int gpu_pm_qos_command(struct exynos_context *platform, gpu_pmqos_state state)
                if (!platform->pmqos_int_disable)
                        pm_qos_update_request(&exynos5_g3d_int_qos, 0);
                pm_qos_update_request(&exynos5_g3d_cpu_cluster0_min_qos, 0);
-               pm_qos_update_request(&exynos5_g3d_cpu_cluster1_max_qos, PM_QOS_CLUSTER1_FREQ_MAX_DEFAULT_VALUE);
+               pm_qos_update_request(&exynos5_g3d_cpu_cluster1_max_qos, PM_QOS_CPU_FREQ_MAX_DEFAULT_VALUE);
                break;
        case GPU_CONTROL_PM_QOS_EGL_SET:
                if (!platform->is_pm_qos_init) {
@@ -120,7 +120,7 @@ int gpu_pm_qos_command(struct exynos_context *platform, gpu_pmqos_state state)
                /* pm_qos_update_request(&exynos5_g3d_cpu_cluster1_min_qos, platform->boost_egl_min_lock); */
                pm_qos_update_request_timeout(&exynos5_g3d_cpu_cluster1_min_qos, platform->boost_egl_min_lock, 30000);
                for (idx = 0; idx < platform->table_size; idx++)
-                       platform->table[idx].cpu_max_freq = PM_QOS_CLUSTER1_FREQ_MAX_DEFAULT_VALUE;
+                       platform->table[idx].cpu_max_freq = PM_QOS_CPU_FREQ_MAX_DEFAULT_VALUE;
                break;
        case GPU_CONTROL_PM_QOS_EGL_RESET:
                if (!platform->is_pm_qos_init) {