MIPS: mipsregs.h: Reorder CP1 macro definitions

Originally CP1 macros were placed between CP0 register name macros and
CP0 register value macros.  As changes were applied to the header the
position of CP1 macros gradually has become more and more arbitrary and
two separate blocks were created.  This may only cause confusion.

Move them out of the way then and place together after all the CP0
macros.  No semantic change.

[ralf@linux-mips.org: Fix conflict.]

Signed-off-by: Maciej W. Rozycki <macro@linux-mips.org>
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/9667/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/mipsregs.h b/arch/mips/include/asm/mipsregs.h
index c7554f057366b9f34ad9161c25d84d35b83c19d8..0e8af630916096f46aef8645465ec91568ad963f 100644 (file)
--- a/arch/mips/include/asm/mipsregs.h
+++ b/arch/mips/include/asm/mipsregs.h
@@ -111,66 +111,6 @@
  */
 #define CP0_TX39_CACHE $7
 
-/*
- * Coprocessor 1 (FPU) register names
- */
-#define CP1_REVISION   $0
-#define CP1_STATUS     $31
-
-/*
- * FPU Status Register Values
- */
-#define FPU_CSR_FLUSH  0x01000000      /* flush denormalised results to 0 */
-#define FPU_CSR_COND   0x00800000      /* $fcc0 */
-#define FPU_CSR_COND0  0x00800000      /* $fcc0 */
-#define FPU_CSR_COND1  0x02000000      /* $fcc1 */
-#define FPU_CSR_COND2  0x04000000      /* $fcc2 */
-#define FPU_CSR_COND3  0x08000000      /* $fcc3 */
-#define FPU_CSR_COND4  0x10000000      /* $fcc4 */
-#define FPU_CSR_COND5  0x20000000      /* $fcc5 */
-#define FPU_CSR_COND6  0x40000000      /* $fcc6 */
-#define FPU_CSR_COND7  0x80000000      /* $fcc7 */
-
-/*
- * Bits 18 - 20 of the FPU Status Register will be read as 0,
- * and should be written as zero.
- */
-#define FPU_CSR_RSVD   0x001c0000
-
-/*
- * X the exception cause indicator
- * E the exception enable
- * S the sticky/flag bit
-*/
-#define FPU_CSR_ALL_X  0x0003f000
-#define FPU_CSR_UNI_X  0x00020000
-#define FPU_CSR_INV_X  0x00010000
-#define FPU_CSR_DIV_X  0x00008000
-#define FPU_CSR_OVF_X  0x00004000
-#define FPU_CSR_UDF_X  0x00002000
-#define FPU_CSR_INE_X  0x00001000
-
-#define FPU_CSR_ALL_E  0x00000f80
-#define FPU_CSR_INV_E  0x00000800
-#define FPU_CSR_DIV_E  0x00000400
-#define FPU_CSR_OVF_E  0x00000200
-#define FPU_CSR_UDF_E  0x00000100
-#define FPU_CSR_INE_E  0x00000080
-
-#define FPU_CSR_ALL_S  0x0000007c
-#define FPU_CSR_INV_S  0x00000040
-#define FPU_CSR_DIV_S  0x00000020
-#define FPU_CSR_OVF_S  0x00000010
-#define FPU_CSR_UDF_S  0x00000008
-#define FPU_CSR_INE_S  0x00000004
-
-/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
-#define FPU_CSR_RM     0x00000003
-#define FPU_CSR_RN     0x0     /* nearest */
-#define FPU_CSR_RZ     0x1     /* towards zero */
-#define FPU_CSR_RU     0x2     /* towards +Infinity */
-#define FPU_CSR_RD     0x3     /* towards -Infinity */
-
 
 /*
  * Values for PageMask register
@@ -686,18 +626,6 @@
 #define MIPS_CMGCRB_BASE       11
 #define MIPS_CMGCRF_BASE       (~_ULCAST_((1 << MIPS_CMGCRB_BASE) - 1))
 
-/*
- * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
- */
-#define MIPS_FPIR_S            (_ULCAST_(1) << 16)
-#define MIPS_FPIR_D            (_ULCAST_(1) << 17)
-#define MIPS_FPIR_PS           (_ULCAST_(1) << 18)
-#define MIPS_FPIR_3D           (_ULCAST_(1) << 19)
-#define MIPS_FPIR_W            (_ULCAST_(1) << 20)
-#define MIPS_FPIR_L            (_ULCAST_(1) << 21)
-#define MIPS_FPIR_F64          (_ULCAST_(1) << 22)
-#define MIPS_FPIR_FREP         (_ULCAST_(1) << 29)
-
 /*
  * Bits in the MIPS32 Memory Segmentation registers.
  */
@@ -757,6 +685,81 @@
 #define MIPS_CDMMBASE_ADDR_SHIFT 11
 #define MIPS_CDMMBASE_ADDR_START 15
 
+
+/*
+ * Coprocessor 1 (FPU) register names
+ */
+#define CP1_REVISION   $0
+#define CP1_STATUS     $31
+
+
+/*
+ * Bits in the MIPS32/64 coprocessor 1 (FPU) revision register.
+ */
+#define MIPS_FPIR_S            (_ULCAST_(1) << 16)
+#define MIPS_FPIR_D            (_ULCAST_(1) << 17)
+#define MIPS_FPIR_PS           (_ULCAST_(1) << 18)
+#define MIPS_FPIR_3D           (_ULCAST_(1) << 19)
+#define MIPS_FPIR_W            (_ULCAST_(1) << 20)
+#define MIPS_FPIR_L            (_ULCAST_(1) << 21)
+#define MIPS_FPIR_F64          (_ULCAST_(1) << 22)
+#define MIPS_FPIR_FREP         (_ULCAST_(1) << 29)
+
+/*
+ * FPU Status Register Values
+ */
+#define FPU_CSR_FLUSH  0x01000000      /* flush denormalised results to 0 */
+#define FPU_CSR_COND   0x00800000      /* $fcc0 */
+#define FPU_CSR_COND0  0x00800000      /* $fcc0 */
+#define FPU_CSR_COND1  0x02000000      /* $fcc1 */
+#define FPU_CSR_COND2  0x04000000      /* $fcc2 */
+#define FPU_CSR_COND3  0x08000000      /* $fcc3 */
+#define FPU_CSR_COND4  0x10000000      /* $fcc4 */
+#define FPU_CSR_COND5  0x20000000      /* $fcc5 */
+#define FPU_CSR_COND6  0x40000000      /* $fcc6 */
+#define FPU_CSR_COND7  0x80000000      /* $fcc7 */
+
+/*
+ * Bits 18 - 20 of the FPU Status Register will be read as 0,
+ * and should be written as zero.
+ */
+#define FPU_CSR_RSVD   0x001c0000
+
+/*
+ * X the exception cause indicator
+ * E the exception enable
+ * S the sticky/flag bit
+*/
+#define FPU_CSR_ALL_X  0x0003f000
+#define FPU_CSR_UNI_X  0x00020000
+#define FPU_CSR_INV_X  0x00010000
+#define FPU_CSR_DIV_X  0x00008000
+#define FPU_CSR_OVF_X  0x00004000
+#define FPU_CSR_UDF_X  0x00002000
+#define FPU_CSR_INE_X  0x00001000
+
+#define FPU_CSR_ALL_E  0x00000f80
+#define FPU_CSR_INV_E  0x00000800
+#define FPU_CSR_DIV_E  0x00000400
+#define FPU_CSR_OVF_E  0x00000200
+#define FPU_CSR_UDF_E  0x00000100
+#define FPU_CSR_INE_E  0x00000080
+
+#define FPU_CSR_ALL_S  0x0000007c
+#define FPU_CSR_INV_S  0x00000040
+#define FPU_CSR_DIV_S  0x00000020
+#define FPU_CSR_OVF_S  0x00000010
+#define FPU_CSR_UDF_S  0x00000008
+#define FPU_CSR_INE_S  0x00000004
+
+/* Bits 0 and 1 of FPU Status Register specify the rounding mode */
+#define FPU_CSR_RM     0x00000003
+#define FPU_CSR_RN     0x0     /* nearest */
+#define FPU_CSR_RZ     0x1     /* towards zero */
+#define FPU_CSR_RU     0x2     /* towards +Infinity */
+#define FPU_CSR_RD     0x3     /* towards -Infinity */
+
+
 #ifndef __ASSEMBLY__
 
 /*