drm/nouveau/msppp: rename from ppp (no binary change)

Switch to NVIDIA's name for the device.

The namespace of NVKM is being changed to nvkm_ instead of nouveau_,
which will be used for the DRM part of the driver.  This is being
done in order to make it very clear as to what part of the driver a
given symbol belongs to, and as a minor step towards splitting the
DRM driver out to be able to stand on its own (for virt).

Because there's already a large amount of churn here anyway, this is
as good a time as any to also switch to NVIDIA's device and chipset
naming to ease collaboration with them.

A comparison of objdump disassemblies proves no code changes.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/include/nvif/class.h b/drivers/gpu/drm/nouveau/include/nvif/class.h
index c88bb7c1010ede4f951008da084453ffea1747b8..e35988aa255b00bb670135bf5e248ca183f60921 100644 (file)
--- a/drivers/gpu/drm/nouveau/include/nvif/class.h
+++ b/drivers/gpu/drm/nouveau/include/nvif/class.h
@@ -128,7 +128,7 @@ struct nv_device_v0 {
 #define NV_DEVICE_V0_DISABLE_VP                           0x0000000800000000ULL
 #define NV_DEVICE_V0_DISABLE_CIPHER                       0x0000001000000000ULL
 #define NV_DEVICE_V0_DISABLE_BSP                          0x0000002000000000ULL
-#define NV_DEVICE_V0_DISABLE_PPP                          0x0000004000000000ULL
+#define NV_DEVICE_V0_DISABLE_MSPPP                        0x0000004000000000ULL
 #define NV_DEVICE_V0_DISABLE_CE0                          0x0000008000000000ULL
 #define NV_DEVICE_V0_DISABLE_CE1                          0x0000010000000000ULL
 #define NV_DEVICE_V0_DISABLE_VIC                          0x0000020000000000ULL
@@ -349,7 +349,7 @@ struct kepler_channel_gpfifo_a_v0 {
        __u8  version;
 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_GR                               0x01
 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_VP                               0x02
-#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_PPP                              0x04
+#define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSPPP                            0x04
 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_MSVLD                            0x08
 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE0                              0x10
 #define KEPLER_CHANNEL_GPFIFO_A_V0_ENGINE_CE1                              0x20

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
index 3d87d3daa5a81e5fd5ae675d469a866d7670e33e..1a6a49c7f84bfff705568e7794e0f8d7899feef4 100644 (file)
--- a/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
+++ b/drivers/gpu/drm/nouveau/include/nvkm/core/device.h
@@ -51,7 +51,7 @@ enum nv_subdev_type {
        NVDEV_ENGINE_VP,
        NVDEV_ENGINE_CIPHER,
        NVDEV_ENGINE_BSP,
-       NVDEV_ENGINE_PPP,
+       NVDEV_ENGINE_MSPPP,
        NVDEV_ENGINE_CE0,
        NVDEV_ENGINE_CE1,
        NVDEV_ENGINE_CE2,

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
new file mode 100644 (file)
index 0000000..5f2f82e
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/include/nvkm/engine/msppp.h
@@ -0,0 +1,7 @@
+#ifndef __NOUVEAU_MSPPP_H__
+#define __NOUVEAU_MSPPP_H__
+
+extern struct nouveau_oclass nv98_msppp_oclass;
+extern struct nouveau_oclass nvc0_msppp_oclass;
+
+#endif

diff --git a/drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h b/drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
deleted file mode 100644 (file)
index 0a66781..0000000
--- a/drivers/gpu/drm/nouveau/include/nvkm/engine/ppp.h
+++ /dev/null
@@ -1,7 +0,0 @@
-#ifndef __NOUVEAU_PPP_H__
-#define __NOUVEAU_PPP_H__
-
-extern struct nouveau_oclass nv98_ppp_oclass;
-extern struct nouveau_oclass nvc0_ppp_oclass;
-
-#endif

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
index 16c3a91b7e4a7465edc4257014348b3b73ec0ebe..0607d595f6e77c9a3e3d907e5308da660656e33d 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/Kbuild
@@ -12,7 +12,7 @@ include $(src)/nvkm/engine/gr/Kbuild
 include $(src)/nvkm/engine/mpeg/Kbuild
 include $(src)/nvkm/engine/msvld/Kbuild
 include $(src)/nvkm/engine/pm/Kbuild
-include $(src)/nvkm/engine/ppp/Kbuild
+include $(src)/nvkm/engine/msppp/Kbuild
 include $(src)/nvkm/engine/sec/Kbuild
 include $(src)/nvkm/engine/software/Kbuild
 include $(src)/nvkm/engine/vp/Kbuild

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
index 5b226cb042984beeff674473c8fd7ad10d764f50..fda8d729aa307b885f6b9ffbccb7550faf45132a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/base.c
@@ -234,7 +234,7 @@ static const u64 disable_map[] = {
        [NVDEV_ENGINE_VP]       = NV_DEVICE_V0_DISABLE_VP,
        [NVDEV_ENGINE_CIPHER]   = NV_DEVICE_V0_DISABLE_CIPHER,
        [NVDEV_ENGINE_BSP]      = NV_DEVICE_V0_DISABLE_BSP,
-       [NVDEV_ENGINE_PPP]      = NV_DEVICE_V0_DISABLE_PPP,
+       [NVDEV_ENGINE_MSPPP]    = NV_DEVICE_V0_DISABLE_MSPPP,
        [NVDEV_ENGINE_CE0]      = NV_DEVICE_V0_DISABLE_CE0,
        [NVDEV_ENGINE_CE1]      = NV_DEVICE_V0_DISABLE_CE1,
        [NVDEV_ENGINE_CE2]      = NV_DEVICE_V0_DISABLE_CE2,

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
index 2ea1dbcf641f8f17b8b01d67f19814ff34e373a5..69025050333248406052ed73451d794a8f2ddc89 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/gm100.c
@@ -52,7 +52,7 @@
 #include <engine/bsp.h>
 #include <engine/msvld.h>
 #include <engine/vp.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
 #include <engine/pm.h>
 
 int
@@ -96,7 +96,7 @@ gm100_identify(struct nouveau_device *device)
 #if 0
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 #endif
                break;
        case 0x124:
@@ -139,7 +139,7 @@ gm100_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &gm204_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
 #endif
                break;
        default:

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
index 6e5ccb3713721d4d7a922131696fdbde9e12ab0f..3f3d2ea1a93051be20c044d9911f75094a8746f1 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nv50.c
@@ -51,7 +51,7 @@
 #include <engine/sec.h>
 #include <engine/bsp.h>
 #include <engine/msvld.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
 #include <engine/ce.h>
 #include <engine/disp.h>
 #include <engine/pm.h>
@@ -256,7 +256,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
                break;
@@ -314,7 +314,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
                break;
@@ -343,7 +343,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                device->oclass[NVDEV_ENGINE_SEC    ] = &nv98_sec_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nv94_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nv84_pm_oclass;
                break;
@@ -373,7 +373,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_MPEG   ] = &nv84_mpeg_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nva3_ce_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
@@ -403,7 +403,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nva3_ce_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
@@ -433,7 +433,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nva3_ce_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;
@@ -463,7 +463,7 @@ nv50_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] = &nv50_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nv98_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nv98_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nv98_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nv98_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nva3_ce_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] =  nva3_pm_oclass;

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
index d159d29930439cf4e0afe52d71ad82dc6124cc1b..b241421e76a25913703917333ea002c6a9ceb58a 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nvc0.c
@@ -50,7 +50,7 @@
 #include <engine/vp.h>
 #include <engine/bsp.h>
 #include <engine/msvld.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
 #include <engine/ce.h>
 #include <engine/disp.h>
 #include <engine/pm.h>
@@ -86,7 +86,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvc0_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_CE1    ] = &nvc0_ce1_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
@@ -119,7 +119,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_CE1    ] = &nvc0_ce1_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
@@ -152,7 +152,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -184,7 +184,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_CE1    ] = &nvc0_ce1_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
@@ -217,7 +217,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvc4_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -249,7 +249,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvc1_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -281,7 +281,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvc8_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_CE1    ] = &nvc0_ce1_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nva3_disp_oclass;
@@ -314,7 +314,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvd9_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nvd0_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;
@@ -344,7 +344,7 @@ nvc0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_GR     ] =  nvd7_gr_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nvc0_vp_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nvc0_msvld_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_CE0    ] = &nvc0_ce0_oclass;
                device->oclass[NVDEV_ENGINE_DISP   ] =  nvd0_disp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nvc0_pm_oclass;

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
index c68e76b40d5145c0a0af6129ef18a340fe352727..df975987b9ca73f4e60bbb6880c45c22df3b8142 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/device/nve0.c
@@ -52,7 +52,7 @@
 #include <engine/bsp.h>
 #include <engine/msvld.h>
 #include <engine/vp.h>
-#include <engine/ppp.h>
+#include <engine/msppp.h>
 #include <engine/pm.h>
 
 int
@@ -90,7 +90,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nve0_pm_oclass;
                break;
        case 0xe7:
@@ -124,7 +124,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nve0_pm_oclass;
                break;
        case 0xe6:
@@ -158,7 +158,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nve0_pm_oclass;
                break;
        case 0xea:
@@ -214,7 +214,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nvf0_pm_oclass;
                break;
        case 0xf1:
@@ -248,7 +248,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                device->oclass[NVDEV_ENGINE_PM     ] = &nvf0_pm_oclass;
                break;
        case 0x106:
@@ -282,7 +282,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                break;
        case 0x108:
                device->cname = "GK208";
@@ -315,7 +315,7 @@ nve0_identify(struct nouveau_device *device)
                device->oclass[NVDEV_ENGINE_CE2    ] = &nve0_ce2_oclass;
                device->oclass[NVDEV_ENGINE_MSVLD  ] = &nve0_msvld_oclass;
                device->oclass[NVDEV_ENGINE_VP     ] = &nve0_vp_oclass;
-               device->oclass[NVDEV_ENGINE_PPP    ] = &nvc0_ppp_oclass;
+               device->oclass[NVDEV_ENGINE_MSPPP  ] = &nvc0_msppp_oclass;
                break;
        default:
                nv_fatal(device, "unknown Kepler chipset\n");

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
index 4a3638e1944e3bb1d744fb1f3bf92fa4bbda9116..6abcd5c3e773b28438688e8f6b410166797645fe 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nv84.c
@@ -58,7 +58,7 @@ nv84_fifo_context_attach(struct nouveau_object *parent,
        case NVDEV_ENGINE_SW    : return 0;
        case NVDEV_ENGINE_GR    : addr = 0x0020; break;
        case NVDEV_ENGINE_VP    : addr = 0x0040; break;
-       case NVDEV_ENGINE_PPP   :
+       case NVDEV_ENGINE_MSPPP :
        case NVDEV_ENGINE_MPEG  : addr = 0x0060; break;
        case NVDEV_ENGINE_BSP   :
        case NVDEV_ENGINE_MSVLD : addr = 0x0080; break;
@@ -96,7 +96,7 @@ nv84_fifo_context_detach(struct nouveau_object *parent, bool suspend,
        case NVDEV_ENGINE_SW    : return 0;
        case NVDEV_ENGINE_GR    : engn = 0; addr = 0x0020; break;
        case NVDEV_ENGINE_VP    : engn = 3; addr = 0x0040; break;
-       case NVDEV_ENGINE_PPP   :
+       case NVDEV_ENGINE_MSPPP :
        case NVDEV_ENGINE_MPEG  : engn = 1; addr = 0x0060; break;
        case NVDEV_ENGINE_BSP   :
        case NVDEV_ENGINE_MSVLD : engn = 5; addr = 0x0080; break;
@@ -145,7 +145,7 @@ nv84_fifo_object_attach(struct nouveau_object *parent,
        case NVDEV_ENGINE_SW    : context |= 0x00000000; break;
        case NVDEV_ENGINE_GR    : context |= 0x00100000; break;
        case NVDEV_ENGINE_MPEG  :
-       case NVDEV_ENGINE_PPP   : context |= 0x00200000; break;
+       case NVDEV_ENGINE_MSPPP : context |= 0x00200000; break;
        case NVDEV_ENGINE_ME    :
        case NVDEV_ENGINE_CE0   : context |= 0x00300000; break;
        case NVDEV_ENGINE_VP    : context |= 0x00400000; break;
@@ -195,7 +195,7 @@ nv84_fifo_chan_ctor_dma(struct nouveau_object *parent,
                                          (1ULL << NVDEV_ENGINE_SEC) |
                                          (1ULL << NVDEV_ENGINE_BSP) |
                                          (1ULL << NVDEV_ENGINE_MSVLD) |
-                                         (1ULL << NVDEV_ENGINE_PPP) |
+                                         (1ULL << NVDEV_ENGINE_MSPPP) |
                                          (1ULL << NVDEV_ENGINE_CE0) |
                                          (1ULL << NVDEV_ENGINE_VIC), &chan);
        *pobject = nv_object(chan);
@@ -270,7 +270,7 @@ nv84_fifo_chan_ctor_ind(struct nouveau_object *parent,
                                          (1ULL << NVDEV_ENGINE_SEC) |
                                          (1ULL << NVDEV_ENGINE_BSP) |
                                          (1ULL << NVDEV_ENGINE_MSVLD) |
-                                         (1ULL << NVDEV_ENGINE_PPP) |
+                                         (1ULL << NVDEV_ENGINE_MSPPP) |
                                          (1ULL << NVDEV_ENGINE_CE0) |
                                          (1ULL << NVDEV_ENGINE_VIC), &chan);
        *pobject = nv_object(chan);

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
index 1511e387fd5d0623f4c584edf0fcfd5719bfa7cb..d86601c02368fc39cb8354cccbdc8c25a915f107 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nvc0.c
@@ -126,7 +126,7 @@ nvc0_fifo_context_attach(struct nouveau_object *parent,
        case NVDEV_ENGINE_CE1  : addr = 0x0240; break;
        case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
        case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-       case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+       case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
        default:
                return -EINVAL;
        }
@@ -163,7 +163,7 @@ nvc0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
        case NVDEV_ENGINE_CE1  : addr = 0x0240; break;
        case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
        case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-       case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+       case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
        default:
                return -EINVAL;
        }
@@ -216,7 +216,7 @@ nvc0_fifo_chan_ctor(struct nouveau_object *parent,
                                          (1ULL << NVDEV_ENGINE_CE1) |
                                          (1ULL << NVDEV_ENGINE_MSVLD) |
                                          (1ULL << NVDEV_ENGINE_VP) |
-                                         (1ULL << NVDEV_ENGINE_PPP), &chan);
+                                         (1ULL << NVDEV_ENGINE_MSPPP), &chan);
        *pobject = nv_object(chan);
        if (ret)
                return ret;
@@ -383,7 +383,7 @@ nvc0_fifo_engidx(struct nvc0_fifo_priv *priv, u32 engn)
        switch (engn) {
        case NVDEV_ENGINE_GR   : engn = 0; break;
        case NVDEV_ENGINE_MSVLD: engn = 1; break;
-       case NVDEV_ENGINE_PPP  : engn = 2; break;
+       case NVDEV_ENGINE_MSPPP: engn = 2; break;
        case NVDEV_ENGINE_VP   : engn = 3; break;
        case NVDEV_ENGINE_CE0  : engn = 4; break;
        case NVDEV_ENGINE_CE1  : engn = 5; break;
@@ -400,7 +400,7 @@ nvc0_fifo_engine(struct nvc0_fifo_priv *priv, u32 engn)
        switch (engn) {
        case 0: engn = NVDEV_ENGINE_GR; break;
        case 1: engn = NVDEV_ENGINE_MSVLD; break;
-       case 2: engn = NVDEV_ENGINE_PPP; break;
+       case 2: engn = NVDEV_ENGINE_MSPPP; break;
        case 3: engn = NVDEV_ENGINE_VP; break;
        case 4: engn = NVDEV_ENGINE_CE0; break;
        case 5: engn = NVDEV_ENGINE_CE1; break;
@@ -549,7 +549,7 @@ nvc0_fifo_fault_engine[] = {
        { 0x05, "BAR3", NULL, NVDEV_SUBDEV_INSTMEM },
        { 0x07, "PFIFO", NULL, NVDEV_ENGINE_FIFO },
        { 0x10, "PMSVLD", NULL, NVDEV_ENGINE_MSVLD },
-       { 0x11, "PPPP", NULL, NVDEV_ENGINE_PPP },
+       { 0x11, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
        { 0x13, "PCOUNTER" },
        { 0x14, "PVP", NULL, NVDEV_ENGINE_VP },
        { 0x15, "PCE0", NULL, NVDEV_ENGINE_CE0 },
@@ -582,7 +582,7 @@ nvc0_fifo_fault_hubclient[] = {
        { 0x07, "BAR_READ" },
        { 0x08, "BAR_WRITE" },
        { 0x0b, "PVP" },
-       { 0x0c, "PPPP" },
+       { 0x0c, "PMSPPP" },
        { 0x0d, "PMSVLD" },
        { 0x11, "PCOUNTER" },
        { 0x12, "PDAEMON" },
@@ -940,7 +940,7 @@ nvc0_fifo_init(struct nouveau_object *object)
        if (priv->spoon_nr >= 3) {
                nv_wr32(priv, 0x002208, ~(1 << 0)); /* PGRAPH */
                nv_wr32(priv, 0x00220c, ~(1 << 1)); /* PVP */
-               nv_wr32(priv, 0x002210, ~(1 << 1)); /* PPP */
+               nv_wr32(priv, 0x002210, ~(1 << 1)); /* PMSPP */
                nv_wr32(priv, 0x002214, ~(1 << 1)); /* PMSVLD */
                nv_wr32(priv, 0x002218, ~(1 << 2)); /* PCE0 */
                nv_wr32(priv, 0x00221c, ~(1 << 1)); /* PCE1 */

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
index 324008e8fa9b8a3ed13d7d3abb9130c56154bcdd..81dc280c0022e35a8cb82defa615f78785c30fb0 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/fifo/nve0.c
@@ -49,7 +49,7 @@ static const struct {
        _(NVDEV_ENGINE_GR      , (1ULL << NVDEV_ENGINE_SW) |
                                 (1ULL << NVDEV_ENGINE_CE2)),
        _(NVDEV_ENGINE_VP      , 0),
-       _(NVDEV_ENGINE_PPP     , 0),
+       _(NVDEV_ENGINE_MSPPP   , 0),
        _(NVDEV_ENGINE_MSVLD   , 0),
        _(NVDEV_ENGINE_CE0     , 0),
        _(NVDEV_ENGINE_CE1     , 0),
@@ -151,7 +151,7 @@ nve0_fifo_context_attach(struct nouveau_object *parent,
        case NVDEV_ENGINE_GR   : addr = 0x0210; break;
        case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
        case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-       case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+       case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
        default:
                return -EINVAL;
        }
@@ -189,7 +189,7 @@ nve0_fifo_context_detach(struct nouveau_object *parent, bool suspend,
        case NVDEV_ENGINE_GR   : addr = 0x0210; break;
        case NVDEV_ENGINE_MSVLD: addr = 0x0270; break;
        case NVDEV_ENGINE_VP   : addr = 0x0250; break;
-       case NVDEV_ENGINE_PPP  : addr = 0x0260; break;
+       case NVDEV_ENGINE_MSPPP: addr = 0x0260; break;
        default:
                return -EINVAL;
        }
@@ -417,7 +417,7 @@ nve0_fifo_engidx(struct nve0_fifo_priv *priv, u32 engn)
        case NVDEV_ENGINE_GR   :
        case NVDEV_ENGINE_CE2  : engn = 0; break;
        case NVDEV_ENGINE_MSVLD: engn = 1; break;
-       case NVDEV_ENGINE_PPP  : engn = 2; break;
+       case NVDEV_ENGINE_MSPPP: engn = 2; break;
        case NVDEV_ENGINE_VP   : engn = 3; break;
        case NVDEV_ENGINE_CE0  : engn = 4; break;
        case NVDEV_ENGINE_CE1  : engn = 5; break;
@@ -620,7 +620,7 @@ nve0_fifo_fault_engine[] = {
        { 0x08, "PBDMA1", NULL, NVDEV_ENGINE_FIFO },
        { 0x09, "PBDMA2", NULL, NVDEV_ENGINE_FIFO },
        { 0x10, "MSVLD", NULL, NVDEV_ENGINE_MSVLD },
-       { 0x11, "MSPPP", NULL, NVDEV_ENGINE_PPP },
+       { 0x11, "MSPPP", NULL, NVDEV_ENGINE_MSPPP },
        { 0x13, "PERF" },
        { 0x14, "MSPDEC", NULL, NVDEV_ENGINE_VP },
        { 0x15, "CE0", NULL, NVDEV_ENGINE_CE0 },

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
new file mode 100644 (file)
index 0000000..9b90ce9
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/Kbuild
@@ -0,0 +1,2 @@
+nvkm-y += nvkm/engine/msppp/nv98.o
+nvkm-y += nvkm/engine/msppp/nvc0.o

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
new file mode 100644 (file)
index 0000000..c044943
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nv98.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2012 Red Hat Inc.
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
+ */
+
+#include <engine/falcon.h>
+#include <engine/msppp.h>
+
+struct nv98_msppp_priv {
+       struct nouveau_falcon base;
+};
+
+/*******************************************************************************
+ * MSPPP object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_msppp_sclass[] = {
+       { 0x88b3, &nouveau_object_ofuncs },
+       { 0x85b3, &nouveau_object_ofuncs },
+       {},
+};
+
+/*******************************************************************************
+ * PMSPPP context
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nv98_msppp_cclass = {
+       .handle = NV_ENGCTX(MSPPP, 0x98),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = _nouveau_falcon_context_ctor,
+               .dtor = _nouveau_falcon_context_dtor,
+               .init = _nouveau_falcon_context_init,
+               .fini = _nouveau_falcon_context_fini,
+               .rd32 = _nouveau_falcon_context_rd32,
+               .wr32 = _nouveau_falcon_context_wr32,
+       },
+};
+
+/*******************************************************************************
+ * PMSPPP engine/subdev functions
+ ******************************************************************************/
+
+static int
+nv98_msppp_init(struct nouveau_object *object)
+{
+       struct nv98_msppp_priv *priv = (void *)object;
+       int ret;
+
+       ret = nouveau_falcon_init(&priv->base);
+       if (ret)
+               return ret;
+
+       nv_wr32(priv, 0x086010, 0x0000ffd2);
+       nv_wr32(priv, 0x08601c, 0x0000fff2);
+       return 0;
+}
+
+static int
+nv98_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+             struct nouveau_oclass *oclass, void *data, u32 size,
+             struct nouveau_object **pobject)
+{
+       struct nv98_msppp_priv *priv;
+       int ret;
+
+       ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
+                                   "PMSPPP", "msppp", &priv);
+       *pobject = nv_object(priv);
+       if (ret)
+               return ret;
+
+       nv_subdev(priv)->unit = 0x00400002;
+       nv_engine(priv)->cclass = &nv98_msppp_cclass;
+       nv_engine(priv)->sclass = nv98_msppp_sclass;
+       return 0;
+}
+
+struct nouveau_oclass
+nv98_msppp_oclass = {
+       .handle = NV_ENGINE(MSPPP, 0x98),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = nv98_msppp_ctor,
+               .dtor = _nouveau_falcon_dtor,
+               .init = nv98_msppp_init,
+               .fini = _nouveau_falcon_fini,
+               .rd32 = _nouveau_falcon_rd32,
+               .wr32 = _nouveau_falcon_wr32,
+       },
+};

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
new file mode 100644 (file)
index 0000000..91398e6
--- /dev/null
+++ b/drivers/gpu/drm/nouveau/nvkm/engine/msppp/nvc0.c
@@ -0,0 +1,110 @@
+/*
+ * Copyright 2012 Maarten Lankhorst
+ *
+ * Permission is hereby granted, free of charge, to any person obtaining a
+ * copy of this software and associated documentation files (the "Software"),
+ * to deal in the Software without restriction, including without limitation
+ * the rights to use, copy, modify, merge, publish, distribute, sublicense,
+ * and/or sell copies of the Software, and to permit persons to whom the
+ * Software is furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
+ * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
+ * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
+ * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
+ * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
+ * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
+ * OTHER DEALINGS IN THE SOFTWARE.
+ *
+ * Authors: Maarten Lankhorst
+ */
+
+#include <engine/falcon.h>
+#include <engine/msppp.h>
+
+struct nvc0_msppp_priv {
+       struct nouveau_falcon base;
+};
+
+/*******************************************************************************
+ * MSPPP object classes
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nvc0_msppp_sclass[] = {
+       { 0x90b3, &nouveau_object_ofuncs },
+       {},
+};
+
+/*******************************************************************************
+ * PMSPPP context
+ ******************************************************************************/
+
+static struct nouveau_oclass
+nvc0_msppp_cclass = {
+       .handle = NV_ENGCTX(MSPPP, 0xc0),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = _nouveau_falcon_context_ctor,
+               .dtor = _nouveau_falcon_context_dtor,
+               .init = _nouveau_falcon_context_init,
+               .fini = _nouveau_falcon_context_fini,
+               .rd32 = _nouveau_falcon_context_rd32,
+               .wr32 = _nouveau_falcon_context_wr32,
+       },
+};
+
+/*******************************************************************************
+ * PMSPPP engine/subdev functions
+ ******************************************************************************/
+
+static int
+nvc0_msppp_init(struct nouveau_object *object)
+{
+       struct nvc0_msppp_priv *priv = (void *)object;
+       int ret;
+
+       ret = nouveau_falcon_init(&priv->base);
+       if (ret)
+               return ret;
+
+       nv_wr32(priv, 0x086010, 0x0000fff2);
+       nv_wr32(priv, 0x08601c, 0x0000fff2);
+       return 0;
+}
+
+static int
+nvc0_msppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
+             struct nouveau_oclass *oclass, void *data, u32 size,
+             struct nouveau_object **pobject)
+{
+       struct nvc0_msppp_priv *priv;
+       int ret;
+
+       ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
+                                   "PMSPPP", "msppp", &priv);
+       *pobject = nv_object(priv);
+       if (ret)
+               return ret;
+
+       nv_subdev(priv)->unit = 0x00000002;
+       nv_subdev(priv)->intr = nouveau_falcon_intr;
+       nv_engine(priv)->cclass = &nvc0_msppp_cclass;
+       nv_engine(priv)->sclass = nvc0_msppp_sclass;
+       return 0;
+}
+
+struct nouveau_oclass
+nvc0_msppp_oclass = {
+       .handle = NV_ENGINE(MSPPP, 0xc0),
+       .ofuncs = &(struct nouveau_ofuncs) {
+               .ctor = nvc0_msppp_ctor,
+               .dtor = _nouveau_falcon_dtor,
+               .init = nvc0_msppp_init,
+               .fini = _nouveau_falcon_fini,
+               .rd32 = _nouveau_falcon_rd32,
+               .wr32 = _nouveau_falcon_wr32,
+       },
+};

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
deleted file mode 100644 (file)
index 0c1de97..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/Kbuild
+++ /dev/null
@@ -1,2 +0,0 @@
-nvkm-y += nvkm/engine/ppp/nv98.o
-nvkm-y += nvkm/engine/ppp/nvc0.o

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c
deleted file mode 100644 (file)
index 13bf31c..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nv98.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Red Hat Inc.
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Ben Skeggs, Maarten Lankhorst, Ilia Mirkin
- */
-
-#include <engine/falcon.h>
-#include <engine/ppp.h>
-
-struct nv98_ppp_priv {
-       struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * PPP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_ppp_sclass[] = {
-       { 0x88b3, &nouveau_object_ofuncs },
-       { 0x85b3, &nouveau_object_ofuncs },
-       {},
-};
-
-/*******************************************************************************
- * PPPP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nv98_ppp_cclass = {
-       .handle = NV_ENGCTX(PPP, 0x98),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = _nouveau_falcon_context_ctor,
-               .dtor = _nouveau_falcon_context_dtor,
-               .init = _nouveau_falcon_context_init,
-               .fini = _nouveau_falcon_context_fini,
-               .rd32 = _nouveau_falcon_context_rd32,
-               .wr32 = _nouveau_falcon_context_wr32,
-       },
-};
-
-/*******************************************************************************
- * PPPP engine/subdev functions
- ******************************************************************************/
-
-static int
-nv98_ppp_init(struct nouveau_object *object)
-{
-       struct nv98_ppp_priv *priv = (void *)object;
-       int ret;
-
-       ret = nouveau_falcon_init(&priv->base);
-       if (ret)
-               return ret;
-
-       nv_wr32(priv, 0x086010, 0x0000ffd2);
-       nv_wr32(priv, 0x08601c, 0x0000fff2);
-       return 0;
-}
-
-static int
-nv98_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-             struct nouveau_oclass *oclass, void *data, u32 size,
-             struct nouveau_object **pobject)
-{
-       struct nv98_ppp_priv *priv;
-       int ret;
-
-       ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
-                                   "PPPP", "ppp", &priv);
-       *pobject = nv_object(priv);
-       if (ret)
-               return ret;
-
-       nv_subdev(priv)->unit = 0x00400002;
-       nv_engine(priv)->cclass = &nv98_ppp_cclass;
-       nv_engine(priv)->sclass = nv98_ppp_sclass;
-       return 0;
-}
-
-struct nouveau_oclass
-nv98_ppp_oclass = {
-       .handle = NV_ENGINE(PPP, 0x98),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = nv98_ppp_ctor,
-               .dtor = _nouveau_falcon_dtor,
-               .init = nv98_ppp_init,
-               .fini = _nouveau_falcon_fini,
-               .rd32 = _nouveau_falcon_rd32,
-               .wr32 = _nouveau_falcon_wr32,
-       },
-};

diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c
deleted file mode 100644 (file)
index 73719aa..0000000
--- a/drivers/gpu/drm/nouveau/nvkm/engine/ppp/nvc0.c
+++ /dev/null
@@ -1,110 +0,0 @@
-/*
- * Copyright 2012 Maarten Lankhorst
- *
- * Permission is hereby granted, free of charge, to any person obtaining a
- * copy of this software and associated documentation files (the "Software"),
- * to deal in the Software without restriction, including without limitation
- * the rights to use, copy, modify, merge, publish, distribute, sublicense,
- * and/or sell copies of the Software, and to permit persons to whom the
- * Software is furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
- * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
- * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
- * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * Authors: Maarten Lankhorst
- */
-
-#include <engine/falcon.h>
-#include <engine/ppp.h>
-
-struct nvc0_ppp_priv {
-       struct nouveau_falcon base;
-};
-
-/*******************************************************************************
- * PPP object classes
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_ppp_sclass[] = {
-       { 0x90b3, &nouveau_object_ofuncs },
-       {},
-};
-
-/*******************************************************************************
- * PPPP context
- ******************************************************************************/
-
-static struct nouveau_oclass
-nvc0_ppp_cclass = {
-       .handle = NV_ENGCTX(PPP, 0xc0),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = _nouveau_falcon_context_ctor,
-               .dtor = _nouveau_falcon_context_dtor,
-               .init = _nouveau_falcon_context_init,
-               .fini = _nouveau_falcon_context_fini,
-               .rd32 = _nouveau_falcon_context_rd32,
-               .wr32 = _nouveau_falcon_context_wr32,
-       },
-};
-
-/*******************************************************************************
- * PPPP engine/subdev functions
- ******************************************************************************/
-
-static int
-nvc0_ppp_init(struct nouveau_object *object)
-{
-       struct nvc0_ppp_priv *priv = (void *)object;
-       int ret;
-
-       ret = nouveau_falcon_init(&priv->base);
-       if (ret)
-               return ret;
-
-       nv_wr32(priv, 0x086010, 0x0000fff2);
-       nv_wr32(priv, 0x08601c, 0x0000fff2);
-       return 0;
-}
-
-static int
-nvc0_ppp_ctor(struct nouveau_object *parent, struct nouveau_object *engine,
-             struct nouveau_oclass *oclass, void *data, u32 size,
-             struct nouveau_object **pobject)
-{
-       struct nvc0_ppp_priv *priv;
-       int ret;
-
-       ret = nouveau_falcon_create(parent, engine, oclass, 0x086000, true,
-                                   "PPPP", "ppp", &priv);
-       *pobject = nv_object(priv);
-       if (ret)
-               return ret;
-
-       nv_subdev(priv)->unit = 0x00000002;
-       nv_subdev(priv)->intr = nouveau_falcon_intr;
-       nv_engine(priv)->cclass = &nvc0_ppp_cclass;
-       nv_engine(priv)->sclass = nvc0_ppp_sclass;
-       return 0;
-}
-
-struct nouveau_oclass
-nvc0_ppp_oclass = {
-       .handle = NV_ENGINE(PPP, 0xc0),
-       .ofuncs = &(struct nouveau_ofuncs) {
-               .ctor = nvc0_ppp_ctor,
-               .dtor = _nouveau_falcon_dtor,
-               .init = nvc0_ppp_init,
-               .fini = _nouveau_falcon_fini,
-               .rd32 = _nouveau_falcon_rd32,
-               .wr32 = _nouveau_falcon_wr32,
-       },
-};

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
index b27984bbfebb0f0cf06e13b121ae85e8187c56c2..1da2bedce00a319de49b966865cdb4976a7964ca 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nv98.c
@@ -35,7 +35,7 @@ nv98_devinit_disable(struct nouveau_devinit *devinit)
        if (!(r001540 & 0x40000000)) {
                disable |= (1ULL << NVDEV_ENGINE_VP);
                disable |= (1ULL << NVDEV_ENGINE_MSVLD);
-               disable |= (1ULL << NVDEV_ENGINE_PPP);
+               disable |= (1ULL << NVDEV_ENGINE_MSPPP);
        }
 
        if (!(r00154c & 0x00000004))

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
index b116f8040bbc727961ba3cf2d782f4a298649e4c..8bc7668faede854fcd2a4c902ac03ec159721c7b 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nva3.c
@@ -68,7 +68,7 @@ nva3_devinit_disable(struct nouveau_devinit *devinit)
 
        if (!(r001540 & 0x40000000)) {
                disable |= (1ULL << NVDEV_ENGINE_VP);
-               disable |= (1ULL << NVDEV_ENGINE_PPP);
+               disable |= (1ULL << NVDEV_ENGINE_MSPPP);
        }
 
        if (!(r00154c & 0x00000004))

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
index 140c300c70389ac5fcf722d9a8e22eb55cbe43b2..fea3be5145538453a6017723dee2306163723b2f 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvaf.c
@@ -34,7 +34,7 @@ nvaf_devinit_disable(struct nouveau_devinit *devinit)
 
        if (!(r001540 & 0x40000000)) {
                disable |= (1ULL << NVDEV_ENGINE_VP);
-               disable |= (1ULL << NVDEV_ENGINE_PPP);
+               disable |= (1ULL << NVDEV_ENGINE_MSPPP);
        }
 
        if (!(r00154c & 0x00000004))

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
index c7b2311f497eee64ac1ba46da6b6a084253c2b36..4fbe8e9c97f04ca2e3ee2b2fe03c5a86cb4b4160 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/devinit/nvc0.c
@@ -71,7 +71,7 @@ nvc0_devinit_disable(struct nouveau_devinit *devinit)
 
        if (r022500 & 0x00000002) {
                disable |= (1ULL << NVDEV_ENGINE_VP);
-               disable |= (1ULL << NVDEV_ENGINE_PPP);
+               disable |= (1ULL << NVDEV_ENGINE_MSPPP);
        }
 
        if (r022500 & 0x00000004)

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
index be129c3297a3c661b8bddeb32a328eefb57f68df..384d7eee830ad1f766b2ee1fa1977f9b9b1893c9 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/fb/nv50.c
@@ -101,7 +101,7 @@ static const struct nouveau_enum vm_client[] = {
        { 0x00000003, "DISPATCH", vm_dispatch_subclients },
        { 0x00000004, "PFIFO_WRITE", NULL },
        { 0x00000005, "CCACHE", vm_ccache_subclients },
-       { 0x00000006, "PPPP", NULL },
+       { 0x00000006, "PMSPPP", NULL },
        { 0x00000007, "CLIPID", NULL },
        { 0x00000008, "PFIFO_READ", NULL },
        { 0x00000009, "VFETCH", NULL },
@@ -121,7 +121,7 @@ static const struct nouveau_enum vm_engine[] = {
        { 0x00000004, "PEEPHOLE", NULL },
        { 0x00000005, "PFIFO", vm_pfifo_subclients, NVDEV_ENGINE_FIFO },
        { 0x00000006, "BAR", vm_bar_subclients },
-       { 0x00000008, "PPPP", NULL, NVDEV_ENGINE_PPP },
+       { 0x00000008, "PMSPPP", NULL, NVDEV_ENGINE_MSPPP },
        { 0x00000008, "PMPEG", NULL, NVDEV_ENGINE_MPEG },
        { 0x00000009, "PBSP", NULL, NVDEV_ENGINE_BSP },
        { 0x0000000a, "PCRYPT", NULL, NVDEV_ENGINE_CIPHER },

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
index 60b250f34cd2869c219c107148bad6cdbf3c8b81..06fc28b5e8902400ebb362e53c83c157e54cc062 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nv98.c
@@ -27,7 +27,7 @@
 static const struct nouveau_mc_intr
 nv98_mc_intr[] = {
        { 0x04000000, NVDEV_ENGINE_DISP },  /* DISP first, so pageflip timestamps work */
-       { 0x00000001, NVDEV_ENGINE_PPP },
+       { 0x00000001, NVDEV_ENGINE_MSPPP },
        { 0x00000100, NVDEV_ENGINE_FIFO },
        { 0x00001000, NVDEV_ENGINE_GR },
        { 0x00004000, NVDEV_ENGINE_SEC },       /* NV84:NVA3 */

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
index 5217a5a404479cbe8f405716fd9d8692f049a64a..76f440efa76442ff948359f3f130a08e1124a6fe 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mc/nvc0.c
@@ -27,7 +27,7 @@
 const struct nouveau_mc_intr
 nvc0_mc_intr[] = {
        { 0x04000000, NVDEV_ENGINE_DISP },  /* DISP first, so pageflip timestamps work. */
-       { 0x00000001, NVDEV_ENGINE_PPP },
+       { 0x00000001, NVDEV_ENGINE_MSPPP },
        { 0x00000020, NVDEV_ENGINE_CE0 },
        { 0x00000040, NVDEV_ENGINE_CE1 },
        { 0x00000080, NVDEV_ENGINE_CE2 },

diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
index 701b9c4ec869bb91895af57ce558db386ab7ce9f..4ac6eb99d55f876385bd9373f6392004ea556535 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
+++ b/drivers/gpu/drm/nouveau/nvkm/subdev/mmu/nv50.c
@@ -174,7 +174,7 @@ nv50_vm_flush(struct nouveau_vm *vm)
                case NVDEV_ENGINE_GR    : vme = 0x00; break;
                case NVDEV_ENGINE_VP    : vme = 0x01; break;
                case NVDEV_SUBDEV_BAR   : vme = 0x06; break;
-               case NVDEV_ENGINE_PPP   :
+               case NVDEV_ENGINE_MSPPP :
                case NVDEV_ENGINE_MPEG  : vme = 0x08; break;
                case NVDEV_ENGINE_BSP   :
                case NVDEV_ENGINE_MSVLD : vme = 0x09; break;