drm/nv04-nv40: Fix up PCI(E) GART DMA object bus address calculation.
authorFrancisco Jerez <currojerez@riseup.net>
Wed, 8 Dec 2010 01:37:12 +0000 (02:37 +0100)
committerBen Skeggs <bskeggs@redhat.com>
Wed, 8 Dec 2010 05:53:04 +0000 (15:53 +1000)
Signed-off-by: Francisco Jerez <currojerez@riseup.net>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
drivers/gpu/drm/nouveau/nouveau_drv.h
drivers/gpu/drm/nouveau/nouveau_object.c
drivers/gpu/drm/nouveau/nouveau_sgdma.c

index f8931b2d129b730ef7d99e15e617aa0d92ae9a77..8f13906185b278b850d3993a16db4b459fa2b324 100644 (file)
@@ -934,8 +934,8 @@ extern void        nouveau_irq_uninstall(struct drm_device *);
 /* nouveau_sgdma.c */
 extern int nouveau_sgdma_init(struct drm_device *);
 extern void nouveau_sgdma_takedown(struct drm_device *);
-extern int nouveau_sgdma_get_page(struct drm_device *, uint32_t offset,
-                                 uint32_t *page);
+extern uint32_t nouveau_sgdma_get_physical(struct drm_device *,
+                                          uint32_t offset);
 extern struct ttm_backend *nouveau_sgdma_init_ttm(struct drm_device *);
 
 /* nouveau_debugfs.c */
index d1bed40dc4497b167eea913938e92dd3c8caa509..55c9fdcfa67fc3a02517f9308f752ddf26c67508 100644 (file)
@@ -478,7 +478,7 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
        struct drm_nouveau_private *dev_priv = chan->dev->dev_private;
        struct drm_device *dev = chan->dev;
        struct nouveau_gpuobj *obj;
-       u32 page_addr, flags0, flags2;
+       u32 flags0, flags2;
        int ret;
 
        if (dev_priv->card_type >= NV_50) {
@@ -495,12 +495,8 @@ nouveau_gpuobj_dma_new(struct nouveau_channel *chan, int class, u64 base,
                        base  += dev_priv->gart_info.aper_base;
                } else
                if (base != 0) {
-                       ret = nouveau_sgdma_get_page(dev, base, &page_addr);
-                       if (ret)
-                               return ret;
-
+                       base = nouveau_sgdma_get_physical(dev, base);
                        target = NV_MEM_TARGET_PCI;
-                       base   = page_addr;
                } else {
                        nouveau_gpuobj_ref(dev_priv->gart_info.sg_ctxdma, pobj);
                        return 0;
index b57201ab538e42a1e93c324d8c3c8b8f73c48fc8..9a250eb53098716f771f981beb2f749d567ca446 100644 (file)
@@ -267,19 +267,15 @@ nouveau_sgdma_takedown(struct drm_device *dev)
        nouveau_vm_put(&dev_priv->gart_info.vma);
 }
 
-int
-nouveau_sgdma_get_page(struct drm_device *dev, uint32_t offset, uint32_t *page)
+uint32_t
+nouveau_sgdma_get_physical(struct drm_device *dev, uint32_t offset)
 {
        struct drm_nouveau_private *dev_priv = dev->dev_private;
        struct nouveau_gpuobj *gpuobj = dev_priv->gart_info.sg_ctxdma;
-       int pte;
+       int pte = (offset >> NV_CTXDMA_PAGE_SHIFT) + 2;
 
-       pte = (offset >> NV_CTXDMA_PAGE_SHIFT) << 2;
-       if (dev_priv->card_type < NV_50) {
-               *page = nv_ro32(gpuobj, (pte + 8)) & ~NV_CTXDMA_PAGE_MASK;
-               return 0;
-       }
+       BUG_ON(dev_priv->card_type >= NV_50);
 
-       NV_ERROR(dev, "Unimplemented on NV50\n");
-       return -EINVAL;
+       return (nv_ro32(gpuobj, 4 * pte) & ~NV_CTXDMA_PAGE_MASK) |
+               (offset & NV_CTXDMA_PAGE_MASK);
 }