arm64: tegra: Add GPIO controllers on Tegra186

Tegra186 has two GPIO controllers that are no longer compatible with the
controller found on earlier generations. One of these controllers exists
in an always-on partition of the SoC whereas the other can be clock- and
powergated.

Signed-off-by: Thierry Reding <treding@nvidia.com>

diff --git a/arch/arm64/boot/dts/nvidia/tegra186.dtsi b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
index 9577359dedc8014145f43f5a2eea7c22ff30f0d5..a918e10240fde06f6ab50fe2b75f4237d041a25a 100644 (file)
--- a/arch/arm64/boot/dts/nvidia/tegra186.dtsi
+++ b/arch/arm64/boot/dts/nvidia/tegra186.dtsi
@@ -1,3 +1,4 @@
+#include <dt-bindings/gpio/tegra186-gpio.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 
 / {
@@ -6,6 +7,23 @@
        #address-cells = <2>;
        #size-cells = <2>;
 
+       gpio: gpio@2200000 {
+               compatible = "nvidia,tegra186-gpio";
+               reg-names = "security", "gpio";
+               reg = <0x0 0x2200000 0x0 0x10000>,
+                     <0x0 0x2210000 0x0 0x10000>;
+               interrupts = <GIC_SPI  47 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI  50 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI  53 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI  56 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI  59 IRQ_TYPE_LEVEL_HIGH>,
+                            <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>;
+               #interrupt-cells = <2>;
+               interrupt-controller;
+               #gpio-cells = <2>;
+               gpio-controller;
+       };
+
        uarta: serial@3100000 {
                compatible = "nvidia,tegra186-uart", "nvidia,tegra20-uart";
                reg = <0x0 0x03100000 0x0 0x40>;
@@ -274,6 +292,18 @@
                status = "disabled";
        };
 
+       gpio_aon: gpio@c2f0000 {
+               compatible = "nvidia,tegra186-gpio-aon";
+               reg-names = "security", "gpio";
+               reg = <0x0 0xc2f0000 0x0 0x1000>,
+                     <0x0 0xc2f1000 0x0 0x1000>;
+               interrupts = <GIC_SPI 60 IRQ_TYPE_LEVEL_HIGH>;
+               gpio-controller;
+               #gpio-cells = <2>;
+               interrupt-controller;
+               #interrupt-cells = <2>;
+       };
+
        sysram@30000000 {
                compatible = "nvidia,tegra186-sysram", "mmio-sram";
                reg = <0x0 0x30000000 0x0 0x50000>;