clk: exynos4: Export mout_core clock of Exynos4210

This patch enables clock lookup registration for mout_core clock used in
Exynos4210 cpufreq driver.

Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>

diff --git a/drivers/clk/samsung/clk-exynos4.c b/drivers/clk/samsung/clk-exynos4.c
index 5592a78b2edc9e84d93d78f0f1629377ed76cea5..f81888dfc5c7c2505d33a59119ab42ded606b675 100644 (file)
--- a/drivers/clk/samsung/clk-exynos4.c
+++ b/drivers/clk/samsung/clk-exynos4.c
@@ -311,7 +311,8 @@ struct samsung_mux_clock exynos4210_mux_clks[] __initdata = {
        MUX(none, "mout_fimd1", group1_p4210, SRC_LCD1, 0, 4),
        MUX(none, "mout_mipi1", group1_p4210, SRC_LCD1, 12, 4),
        MUX_A(sclk_mpll, "sclk_mpll", mout_mpll_p, SRC_CPU, 8, 1, "sclk_mpll"),
-       MUX(none, "mout_core", mout_core_p4210, SRC_CPU, 16, 1),
+       MUX_A(mout_core, "mout_core", mout_core_p4210,
+                       SRC_CPU, 16, 1, "mout_core"),
        MUX_A(sclk_vpll, "sclk_vpll", sclk_vpll_p4210,
                        SRC_TOP0, 8, 1, "sclk_vpll"),
        MUX(none, "mout_fimc0", group1_p4210, SRC_CAM, 0, 4),