if (!reg->size)
return;
- if (!(cflag & CRTSCTS))
- sci_out(port, SCSPTR, 0x0080); /* Set RTS = 1 */
+ if ((s->cfg->capabilities & SCIx_HAVE_RTSCTS) &&
+ ((!(cflag & CRTSCTS)))) {
+ unsigned short status;
+
+ status = sci_in(port, SCSPTR);
+ status &= ~SCSPTR_CTSIO;
+ status |= SCSPTR_RTSIO;
+ sci_out(port, SCSPTR, status); /* Set RTS = 1 */
+ }
}
static int sci_txfill(struct uart_port *port)
sci_init_pins(port, termios->c_cflag);
- reg = sci_getreg(port, SCFCR);
- if (reg->size) {
- unsigned short ctrl;
+ if (s->cfg->capabilities & SCIx_HAVE_RTSCTS) {
+ reg = sci_getreg(port, SCFCR);
+ if (reg->size) {
+ unsigned short ctrl;
- ctrl = sci_in(port, SCFCR);
- if (termios->c_cflag & CRTSCTS)
- ctrl |= SCFCR_MCE;
- else
- ctrl &= ~SCFCR_MCE;
- sci_out(port, SCFCR, ctrl);
+ ctrl = sci_in(port, SCFCR);
+ if (termios->c_cflag & CRTSCTS)
+ ctrl |= SCFCR_MCE;
+ else
+ ctrl &= ~SCFCR_MCE;
+ sci_out(port, SCFCR, ctrl);
+ }
}
sci_out(port, SCSCR, s->cfg->scscr);
#define SCIF_DEFAULT_ERROR_MASK (SCIF_PER | SCIF_FER | SCIF_ER | SCIF_BRK)
+/* SCSPTR, optional */
+#define SCSPTR_RTSIO (1 << 7)
+#define SCSPTR_CTSIO (1 << 5)
+
/* Offsets into the sci_port->irqs array */
enum {
SCIx_ERI_IRQ,
void (*init_pins)(struct uart_port *, unsigned int cflag);
};
+/*
+ * Port-specific capabilities
+ */
+#define SCIx_HAVE_RTSCTS (1 << 0)
+
/*
* Platform device specific platform_data struct
*/
unsigned int irqs[SCIx_NR_IRQS]; /* ERI, RXI, TXI, BRI */
unsigned int type; /* SCI / SCIF / IRDA */
upf_t flags; /* UPF_* flags */
+ unsigned long capabilities; /* Port features/capabilities */
unsigned int scbrr_algo_id; /* SCBRR calculation algo */
unsigned int scscr; /* SCSCR initialization */