powerpc/book3e: Add ICSWX/ACOP support to Book3e cores like A2
authorJimi Xenidis <jimix@pobox.com>
Thu, 29 Sep 2011 10:55:13 +0000 (10:55 +0000)
committerBenjamin Herrenschmidt <benh@kernel.crashing.org>
Fri, 25 Nov 2011 03:11:28 +0000 (14:11 +1100)
ICSWX is also used by the A2 processor to access coprocessors,
although not all "chips" that contain A2s have coprocessors.

Signed-off-by: Jimi Xenidis <jimix@pobox.com>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
arch/powerpc/include/asm/cputable.h
arch/powerpc/include/asm/mmu-book3e.h
arch/powerpc/include/asm/reg_booke.h
arch/powerpc/kernel/cpu_setup_a2.S
arch/powerpc/platforms/Kconfig.cputype
arch/powerpc/platforms/wsp/Kconfig

index e30442c539ce4b809bbbed925faac847a817554a..7044233124ba4fd11996c4176d910273f1b75673 100644 (file)
@@ -437,7 +437,7 @@ extern const char *powerpc_base_platform;
 #define CPU_FTRS_COMPATIBLE    (CPU_FTR_USE_TB | CPU_FTR_PPCAS_ARCH_V2)
 
 #define CPU_FTRS_A2 (CPU_FTR_USE_TB | CPU_FTR_SMT | CPU_FTR_DBELL | \
-                    CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN)
+                    CPU_FTR_NOEXECUTE | CPU_FTR_NODSISRALIGN | CPU_FTR_ICSWX)
 
 #ifdef __powerpc64__
 #ifdef CONFIG_PPC_BOOK3E
index 0260ea5ec3c22f18137dd9c30156a82e26a093a6..50210b9b014752d4dcc86987e7be92e2e09acd14 100644 (file)
@@ -214,6 +214,10 @@ typedef struct {
        unsigned int    id;
        unsigned int    active;
        unsigned long   vdso_base;
+#ifdef CONFIG_PPC_ICSWX
+       struct spinlock *cop_lockp;     /* guard cop related stuff */
+       unsigned long acop;             /* mask of enabled coprocessor types */
+#endif /* CONFIG_PPC_ICSWX */
 #ifdef CONFIG_PPC_MM_SLICES
        u64 low_slices_psize;   /* SLB page size encodings */
        u64 high_slices_psize;  /* 4 bits per slice for now */
index 03c48e819c8e3ff3bc600242dc85ef9111aca478..500fe1dc43e6de21023672b68ac477450a610663 100644 (file)
 #define SPRN_CSRR1     SPRN_SRR3 /* Critical Save and Restore Register 1 */
 #endif
 
+#ifdef CONFIG_PPC_ICSWX
+#define SPRN_HACOP     0x15F   /* Hypervisor Available Coprocessor Register */
+#endif
+
 /* Bit definitions for CCR1. */
 #define        CCR1_DPC        0x00000100 /* Disable L1 I-Cache/D-Cache parity checking */
 #define        CCR1_TCS        0x00000080 /* Timer Clock Select */
index 7f818feaa7a53dd00ce6989353139b212d706e15..ebc62f42a2372105cb6b6722cb4fbb95d426a35a 100644 (file)
@@ -41,11 +41,16 @@ _GLOBAL(__setup_cpu_a2)
         * core local but doing it always won't hurt
         */
 
-#ifdef CONFIG_PPC_WSP_COPRO
+#ifdef CONFIG_PPC_ICSWX
        /* Make sure ACOP starts out as zero */
        li      r3,0
        mtspr   SPRN_ACOP,r3
 
+       /* Skip the following if we are in Guest mode */
+       mfmsr   r3
+       andis.  r0,r3,MSR_GS@h
+       bne     _icswx_skip_guest
+
        /* Enable icswx instruction */
        mfspr   r3,SPRN_A2_CCR2
        ori     r3,r3,A2_CCR2_ENABLE_ICSWX
@@ -54,7 +59,8 @@ _GLOBAL(__setup_cpu_a2)
        /* Unmask all CTs in HACOP */
        li      r3,-1
        mtspr   SPRN_HACOP,r3
-#endif /* CONFIG_PPC_WSP_COPRO */
+_icswx_skip_guest:
+#endif /* CONFIG_PPC_ICSWX */
 
        /* Enable doorbell */
        mfspr   r3,SPRN_A2_CCR2
index a67105aeeda8aeb54eeac88bcb3f3a23250aa99d..46d2a7c77dc0ea6a49d6c84f33ffc4e240208025 100644 (file)
@@ -236,7 +236,7 @@ config VSX
 
 config PPC_ICSWX
        bool "Support for PowerPC icswx coprocessor instruction"
-       depends on POWER4
+       depends on POWER4 || PPC_A2
        default n
        ---help---
 
index bd560c786ed654f76b6703d2b6eb1e37cc717923..43a3b00261e778f2d78cf932562a4f33d52ec6a7 100644 (file)
@@ -1,6 +1,7 @@
 config PPC_WSP
        bool
        select PPC_A2
+       select PPC_ICSWX
        select PPC_SCOM
        select PPC_XICS
        select PPC_ICP_NATIVE