ath6kl: Fix missing gpio pin 9 configuration
authorVasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com>
Tue, 22 May 2012 07:22:48 +0000 (12:52 +0530)
committerKalle Valo <kvalo@qca.qualcomm.com>
Thu, 24 May 2012 07:11:06 +0000 (10:11 +0300)
GPIO pin 9 also needs to be configured along with other gpio
pins to avoid sdio crc errors. I've not experienced any issue
with missing this particular gpio pin configuration, found dunring
code review. This can potentially improve rx performance.

Signed-off-by: Vasanthakumar Thiagarajan <vthiagar@qca.qualcomm.com>
Signed-off-by: Kalle Valo <kvalo@qca.qualcomm.com>
drivers/net/wireless/ath/ath6kl/init.c
drivers/net/wireless/ath/ath6kl/target.h

index 10de1322e702b24a694e42a4a7c33783accd3f42..241febcd7f7c4b388b8f95ca8da0a40bb66294e4 100644 (file)
@@ -1392,6 +1392,12 @@ static int ath6kl_init_upload(struct ath6kl *ar)
            ar->version.target_ver == AR6003_HW_2_1_1_VERSION) {
                ath6kl_err("temporary war to avoid sdio crc error\n");
 
+               param = 0x28;
+               address = GPIO_BASE_ADDRESS + GPIO_PIN9_ADDRESS;
+               status = ath6kl_bmi_reg_write(ar, address, param);
+               if (status)
+                       return status;
+
                param = 0x20;
 
                address = GPIO_BASE_ADDRESS + GPIO_PIN10_ADDRESS;
index 78e0ef4567a5287d4755f2812d7e41b97e1e6ccf..a98c12ba70c1dfa32aa0d3fbd25a76852d5df22b 100644 (file)
@@ -45,6 +45,7 @@
 #define LPO_CAL_ENABLE_S               20
 #define LPO_CAL_ENABLE                 0x00100000
 
+#define GPIO_PIN9_ADDRESS              0x0000004c
 #define GPIO_PIN10_ADDRESS             0x00000050
 #define GPIO_PIN11_ADDRESS             0x00000054
 #define GPIO_PIN12_ADDRESS             0x00000058