powerpc/fsl_pci: Fix P2P bridge handling for MPC83xx PCIe controllers

It appears that we wrongly calculate dev_base for type1 config cycles.
The thing is: we shouldn't subtract hose->first_busno because PCI core
sets PCI primary, secondary and subordinate bus numbers, and PCIe
controller actually takes the registers into account. So we should use
just bus->number.

Also, according to MPC8315 reference manual, primary bus number should
always remain 0. We have PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS quirk
in indirect_pci.c, but since 83xx is somewhat special, it doesn't use
indirect_pci.c routines, so we have to implement the quirk specifically
for 83xx PCIe controllers.

Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com>
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>

diff --git a/arch/powerpc/sysdev/fsl_pci.c b/arch/powerpc/sysdev/fsl_pci.c
index 4e3a3e345ab33cd5b8d435c3415e244e664f70c7..e1a028c1f18d0a94a415038c343f160309eb034c 100644 (file)
--- a/arch/powerpc/sysdev/fsl_pci.c
+++ b/arch/powerpc/sysdev/fsl_pci.c
@@ -464,8 +464,7 @@ static void __iomem *mpc83xx_pcie_remap_cfg(struct pci_bus *bus,
 {
        struct pci_controller *hose = pci_bus_to_host(bus);
        struct mpc83xx_pcie_priv *pcie = hose->dn->data;
-       u8 bus_no = bus->number - hose->first_busno;
-       u32 dev_base = bus_no << 24 | devfn << 16;
+       u32 dev_base = bus->number << 24 | devfn << 16;
        int ret;
 
        ret = mpc83xx_pcie_exclude_device(bus, devfn);
@@ -515,12 +514,17 @@ static int mpc83xx_pcie_read_config(struct pci_bus *bus, unsigned int devfn,
 static int mpc83xx_pcie_write_config(struct pci_bus *bus, unsigned int devfn,
                                     int offset, int len, u32 val)
 {
+       struct pci_controller *hose = pci_bus_to_host(bus);
        void __iomem *cfg_addr;
 
        cfg_addr = mpc83xx_pcie_remap_cfg(bus, devfn, offset);
        if (!cfg_addr)
                return PCIBIOS_DEVICE_NOT_FOUND;
 
+       /* PPC_INDIRECT_TYPE_SURPRESS_PRIMARY_BUS */
+       if (offset == PCI_PRIMARY_BUS && bus->number == hose->first_busno)
+               val &= 0xffffff00;
+
        switch (len) {
        case 1:
                out_8(cfg_addr, val);