drm/fsl-dcu: add extra clock for pixel clock
authorStefan Agner <stefan@agner.ch>
Tue, 22 Mar 2016 22:45:29 +0000 (15:45 -0700)
committerStefan Agner <stefan@agner.ch>
Tue, 26 Apr 2016 03:27:18 +0000 (20:27 -0700)
The Vybrid DCU variant has two independent clock inputs, one
for the registers (IPG bus clock) and one for the pixel clock.
Support this distinction in the DCU DRM driver while staying
backward compatible for old device trees.

Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stefan Agner <stefan@agner.ch>
Documentation/devicetree/bindings/display/fsl,dcu.txt
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_crtc.c
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.c
drivers/gpu/drm/fsl-dcu/fsl_dcu_drm_drv.h

index ebf1be9ae3936e2bd05437398ed816d00dd6f343..2703cf29dd0410ba1d13da1aa46839f5a87e63dc 100644 (file)
@@ -6,8 +6,11 @@ Required properties:
        * "fsl,vf610-dcu".
 
 - reg:                 Address and length of the register set for dcu.
-- clocks:              From common clock binding: handle to dcu clock.
-- clock-names:         From common clock binding: Shall be "dcu".
+- clocks:              Handle to "dcu" and "pix" clock (in the order below)
+                       This can be the same clock (e.g. LS1021a)
+                       See ../clocks/clock-bindings.txt for details.
+- clock-names:         Should be "dcu" and "pix"
+                       See ../clocks/clock-bindings.txt for details.
 - big-endian           Boolean property, LS1021A DCU registers are big-endian.
 - fsl,panel:           The phandle to panel node.
 
@@ -15,8 +18,8 @@ Examples:
 dcu: dcu@2ce0000 {
        compatible = "fsl,ls1021a-dcu";
        reg = <0x0 0x2ce0000 0x0 0x10000>;
-       clocks = <&platform_clk 0>;
-       clock-names = "dcu";
+       clocks = <&platform_clk 0>, <&platform_clk 0>;
+       clock-names = "dcu", "pix";
        big-endian;
        fsl,panel = <&panel>;
 };
index 4ed7798533f9104bda0b870f7bbaa6c661a43097..87d85faaac6a4533bfae16fd7aa36a942946923e 100644 (file)
@@ -71,7 +71,7 @@ static void fsl_dcu_drm_crtc_mode_set_nofb(struct drm_crtc *crtc)
        unsigned long dcuclk;
 
        index = drm_crtc_index(crtc);
-       dcuclk = clk_get_rate(fsl_dev->clk);
+       dcuclk = clk_get_rate(fsl_dev->pix_clk);
        div = dcuclk / mode->clock / 1000;
 
        /* Configure timings: */
index f2a9c1bb32c0cd7c2a8efbe0dc84b3de51ed7827..f80c116018b5b277a0f49e6c49b2033a99fd90ed 100644 (file)
@@ -331,10 +331,21 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
                return ret;
        }
 
+       fsl_dev->pix_clk = devm_clk_get(dev, "pix");
+       if (IS_ERR(fsl_dev->pix_clk)) {
+               /* legancy binding, use dcu clock as pixel clock */
+               fsl_dev->pix_clk = fsl_dev->clk;
+       }
+       ret = clk_prepare_enable(fsl_dev->pix_clk);
+       if (ret < 0) {
+               dev_err(dev, "failed to enable pix clk\n");
+               goto disable_clk;
+       }
+
        drm = drm_dev_alloc(driver, dev);
        if (!drm) {
                ret = -ENOMEM;
-               goto disable_clk;
+               goto disable_pix_clk;
        }
 
        fsl_dev->dev = dev;
@@ -355,6 +366,8 @@ static int fsl_dcu_drm_probe(struct platform_device *pdev)
 
 unref:
        drm_dev_unref(drm);
+disable_pix_clk:
+       clk_disable_unprepare(fsl_dev->pix_clk);
 disable_clk:
        clk_disable_unprepare(fsl_dev->clk);
        return ret;
@@ -365,6 +378,7 @@ static int fsl_dcu_drm_remove(struct platform_device *pdev)
        struct fsl_dcu_drm_device *fsl_dev = platform_get_drvdata(pdev);
 
        clk_disable_unprepare(fsl_dev->clk);
+       clk_disable_unprepare(fsl_dev->pix_clk);
        drm_put_dev(fsl_dev->drm);
 
        return 0;
index 6413ac9e47699a1e97b8f91531b96ad22987944f..edb210277771243a4b1821604dda323a06c4746d 100644 (file)
@@ -183,6 +183,7 @@ struct fsl_dcu_drm_device {
        struct regmap *regmap;
        int irq;
        struct clk *clk;
+       struct clk *pix_clk;
        /*protects hardware register*/
        spinlock_t irq_lock;
        struct drm_device *drm;