ixgbe: add new bus type for intergrated I/O interface (IOSF)
authorDon Skidmore <donald.c.skidmore@intel.com>
Thu, 18 Jun 2015 17:24:06 +0000 (13:24 -0400)
committerJeff Kirsher <jeffrey.t.kirsher@intel.com>
Tue, 1 Sep 2015 23:56:35 +0000 (16:56 -0700)
With this patch we add support for a new bus type ixgbe_bus_type_internal.
X550em devices use IOSF and not PCIe bus so this new type is to accommodate
them.

Signed-off-by: Donald C Skidmore <donald.c.skidmore@intel.com>
Tested-by: Phil Schmitt <phillip.j.schmitt@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
drivers/net/ethernet/intel/ixgbe/ixgbe_main.c
drivers/net/ethernet/intel/ixgbe/ixgbe_type.h
drivers/net/ethernet/intel/ixgbe/ixgbe_x550.c

index 098c84955a1100c075fe3f587581df2e8568d69a..7e331254e9c9b796f3ad61c9e4849526ae4590fd 100644 (file)
@@ -246,11 +246,19 @@ static inline bool ixgbe_pcie_from_parent(struct ixgbe_hw *hw)
 static void ixgbe_check_minimum_link(struct ixgbe_adapter *adapter,
                                     int expected_gts)
 {
+       struct ixgbe_hw *hw = &adapter->hw;
        int max_gts = 0;
        enum pci_bus_speed speed = PCI_SPEED_UNKNOWN;
        enum pcie_link_width width = PCIE_LNK_WIDTH_UNKNOWN;
        struct pci_dev *pdev;
 
+       /* Some devices are not connected over PCIe and thus do not negotiate
+        * speed. These devices do not have valid bus info, and thus any report
+        * we generate may not be correct.
+        */
+       if (hw->bus.type == ixgbe_bus_type_internal)
+               return;
+
        /* determine whether to use the parent device */
        if (ixgbe_pcie_from_parent(&adapter->hw))
                pdev = adapter->pdev->bus->parent->self;
@@ -8837,9 +8845,10 @@ skip_sriov:
        hw->eeprom.ops.read(hw, 0x2d, &adapter->eeprom_verl);
 
        /* pick up the PCI bus settings for reporting later */
-       hw->mac.ops.get_bus_info(hw);
        if (ixgbe_pcie_from_parent(hw))
                ixgbe_get_parent_bus_info(adapter);
+       else
+                hw->mac.ops.get_bus_info(hw);
 
        /* calculate the expected PCIe bandwidth required for optimal
         * performance. Note that some older parts will never have enough
index 19271e5d20106a1285f5e54a63e741ae43289f28..37df15f9ebc811136acb9a2b3d4e0d6b26bd18e1 100644 (file)
@@ -3067,6 +3067,7 @@ enum ixgbe_bus_type {
        ixgbe_bus_type_pci,
        ixgbe_bus_type_pcix,
        ixgbe_bus_type_pci_express,
+       ixgbe_bus_type_internal,
        ixgbe_bus_type_reserved
 };
 
index dce39be28d5fda65851c502add926491597dc691..96f603f435eeded8e6474c6198fbea27acd8832c 100644 (file)
@@ -620,6 +620,7 @@ static s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw)
  **/
 static s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw)
 {
+       hw->bus.type  = ixgbe_bus_type_internal;
        hw->bus.width = ixgbe_bus_width_unknown;
        hw->bus.speed = ixgbe_bus_speed_unknown;