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MIPS: Octeon: Enable Read Inhibit / eXecute Inhibit on Octeon II.
authorDavid Daney <ddaney@caviumnetworks.com>
Thu, 7 Oct 2010 23:03:46 +0000 (16:03 -0700)
committerRalf Baechle <ralf@linux-mips.org>
Fri, 29 Oct 2010 18:08:38 +0000 (19:08 +0100)
Signed-off-by: David Daney <ddaney@caviumnetworks.com>
Patchwork: http://patchwork.linux-mips.org/patch/1666/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h patch | blob | blame | history

diff --git a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
index c84ed74e3c8a4578886aad1a67fa5c44603e0897..0d5a42b5f47abb4091d3257270b72f80ed1fe3ce 100644 (file)
--- a/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
+++ b/arch/mips/include/asm/mach-cavium-octeon/cpu-feature-overrides.h
@@ -59,7 +59,7 @@
 #define cpu_has_veic           0
 #define cpu_hwrena_impl_bits   0xc0000000
 
-#define kernel_uses_smartmips_rixi (cpu_data[0].cputype == CPU_CAVIUM_OCTEON_PLUS)
+#define kernel_uses_smartmips_rixi (cpu_data[0].cputype != CPU_CAVIUM_OCTEON)
 
 #define ARCH_HAS_IRQ_PER_CPU   1
 #define ARCH_HAS_SPINLOCK_PREFETCH 1