}
static const struct musb_platform_ops am35x_ops = {
- .quirks = MUSB_INDEXED_EP,
+ .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
.init = am35x_musb_init,
.exit = am35x_musb_exit,
}
static const struct musb_platform_ops bfin_ops = {
+ .quirks = MUSB_DMA_INVENTRA,
.init = bfin_musb_init,
.exit = bfin_musb_exit,
}
static const struct musb_platform_ops da8xx_ops = {
- .quirks = MUSB_INDEXED_EP,
+ .quirks = MUSB_DMA_CPPI | MUSB_INDEXED_EP,
.init = da8xx_musb_init,
.exit = da8xx_musb_exit,
* mask, state, "vector", and EOI registers.
*/
cppi = container_of(musb->dma_controller, struct cppi, controller);
- if (is_cppi_enabled() && musb->dma_controller && !cppi->irq)
+ if (is_cppi_enabled(musb) && musb->dma_controller && !cppi->irq)
retval = cppi_interrupt(irq, __hci);
/* ack and handle non-CPPI interrupts */
}
static const struct musb_platform_ops davinci_ops = {
+ .quirks = MUSB_DMA_CPPI,
.init = davinci_musb_init,
.exit = davinci_musb_exit,
}
static const struct musb_platform_ops jz4740_musb_ops = {
- .quirks = MUSB_INDEXED_EP,
+ .quirks = MUSB_DMA_INVENTRA | MUSB_INDEXED_EP,
.fifo_mode = 2,
.init = jz4740_musb_init,
.exit = jz4740_musb_exit,
if (!epnum) {
#ifndef CONFIG_USB_TUSB_OMAP_DMA
- if (!is_cppi_enabled()) {
+ if (!is_cppi_enabled(musb)) {
/* endpoint 0 */
if (is_host_active(musb))
musb_h_ep0_irq(musb);
#define is_dma_capable() (1)
#endif
-#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
-#define is_cppi_enabled() 1
+#ifdef CONFIG_USB_UX500_DMA
+#define musb_dma_ux500(musb) (musb->io.quirks & MUSB_DMA_UX500)
+#else
+#define musb_dma_ux500(musb) 0
+#endif
+
+#ifdef CONFIG_USB_TI_CPPI41_DMA
+#define musb_dma_cppi41(musb) (musb->io.quirks & MUSB_DMA_CPPI41)
+#else
+#define musb_dma_cppi41(musb) 0
+#endif
+
+#ifdef CONFIG_USB_TI_CPPI_DMA
+#define musb_dma_cppi(musb) (musb->io.quirks & MUSB_DMA_CPPI)
#else
-#define is_cppi_enabled() 0
+#define musb_dma_cppi(musb) 0
#endif
#ifdef CONFIG_USB_TUSB_OMAP_DMA
-#define tusb_dma_omap() 1
+#define tusb_dma_omap(musb) (musb->io.quirks & MUSB_DMA_TUSB_OMAP)
+#else
+#define tusb_dma_omap(musb) 0
+#endif
+
+#ifdef CONFIG_USB_INVENTRA_DMA
+#define musb_dma_inventra(musb) (musb->io.quirks & MUSB_DMA_INVENTRA)
+#else
+#define musb_dma_inventra(musb) 0
+#endif
+
+#if defined(CONFIG_USB_TI_CPPI_DMA) || defined(CONFIG_USB_TI_CPPI41_DMA)
+#define is_cppi_enabled(musb) \
+ (musb_dma_cppi(musb) || musb_dma_cppi41(musb))
#else
-#define tusb_dma_omap() 0
+#define is_cppi_enabled(musb) 0
#endif
/* Anomaly 05000456 - USB Receive Interrupt Is Not Generated in DMA Mode 1
}
static struct musb_platform_ops dsps_ops = {
- .quirks = MUSB_INDEXED_EP,
+ .quirks = MUSB_DMA_CPPI41 | MUSB_INDEXED_EP,
.init = dsps_musb_init,
.exit = dsps_musb_exit,
}
#endif
- if (is_cppi_enabled()) {
+ if (is_cppi_enabled(musb)) {
/* program endpoint CSR first, then setup DMA */
csr &= ~(MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_TXPKTRDY);
csr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_DMAMODE |
musb_writew(epio, MUSB_TXCSR, csr);
/* invariant: prequest->buf is non-null */
}
- } else if (tusb_dma_omap())
+ } else if (tusb_dma_omap(musb))
use_dma = use_dma && c->channel_program(
musb_ep->dma, musb_ep->packet_sz,
request->zero,
return;
}
- if (is_cppi_enabled() && is_buffer_mapped(req)) {
+ if (is_cppi_enabled(musb) && is_buffer_mapped(req)) {
struct dma_controller *c = musb->dma_controller;
struct dma_channel *channel = musb_ep->dma;
fifo_count = min_t(unsigned, len, fifo_count);
#ifdef CONFIG_USB_TUSB_OMAP_DMA
- if (tusb_dma_omap() && is_buffer_mapped(req)) {
+ if (tusb_dma_omap(musb) && is_buffer_mapped(req)) {
struct dma_controller *c = musb->dma_controller;
struct dma_channel *channel = musb_ep->dma;
u32 dma_addr = request->dma + request->actual;
/* NOTE: no locks here; caller should lock and select EP */
txcsr = musb_readw(ep->regs, MUSB_TXCSR);
txcsr |= MUSB_TXCSR_DMAENAB | MUSB_TXCSR_H_WZC_BITS;
- if (is_cppi_enabled())
+ if (is_cppi_enabled(ep->musb))
txcsr |= MUSB_TXCSR_DMAMODE;
musb_writew(ep->regs, MUSB_TXCSR, txcsr);
}
if (!hw_ep->tx_channel)
musb_h_tx_start(hw_ep);
- else if (is_cppi_enabled() || tusb_dma_omap())
+ else if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
musb_h_tx_dma_start(hw_ep);
}
}
channel->desired_mode = mode;
musb_writew(epio, MUSB_TXCSR, csr);
#else
- if (!is_cppi_enabled() && !tusb_dma_omap())
+ if (!is_cppi_enabled(hw_ep->musb) && !tusb_dma_omap(hw_ep->musb))
return false;
channel->actual_len = 0;
/* kick things off */
- if ((is_cppi_enabled() || tusb_dma_omap()) && dma_channel) {
+ if ((is_cppi_enabled(musb) || tusb_dma_omap(musb)) && dma_channel) {
/* Candidate for DMA */
dma_channel->actual_len = 0L;
qh->segsize = len;
} else if ((usb_pipeisoc(pipe) || transfer_pending) && dma) {
if (musb_tx_dma_program(musb->dma_controller, hw_ep, qh, urb,
offset, length)) {
- if (is_cppi_enabled() || tusb_dma_omap())
+ if (is_cppi_enabled(musb) || tusb_dma_omap(musb))
musb_h_tx_dma_start(hw_ep);
return;
}
}
static const struct musb_platform_ops omap2430_ops = {
+ .quirks = MUSB_DMA_INVENTRA,
.init = omap2430_musb_init,
.exit = omap2430_musb_exit,
dev_dbg(musb->controller, "DMA IRQ %08x\n", dma_src);
real_dma_src = ~real_dma_src & dma_src;
- if (tusb_dma_omap() && real_dma_src) {
+ if (tusb_dma_omap(musb) && real_dma_src) {
int tx_source = (real_dma_src & 0xffff);
int i;
}
static const struct musb_platform_ops tusb_ops = {
- .quirks = MUSB_IN_TUSB,
+ .quirks = MUSB_DMA_TUSB_OMAP | MUSB_IN_TUSB,
.init = tusb_musb_init,
.exit = tusb_musb_exit,
#ifndef __TUSB6010_H__
#define __TUSB6010_H__
-#ifdef CONFIG_USB_TUSB_OMAP_DMA
-#define tusb_dma_omap() 1
-#else
-#define tusb_dma_omap() 0
-#endif
-
/* VLYNQ control register. 32-bit at offset 0x000 */
#define TUSB_VLYNQ_CTRL 0x004
}
static const struct musb_platform_ops ux500_ops = {
- .quirks = MUSB_INDEXED_EP,
+ .quirks = MUSB_DMA_UX500 | MUSB_INDEXED_EP,
.init = ux500_musb_init,
.exit = ux500_musb_exit,
.fifo_mode = 5,