KVM: arm64: vgic-v3: Add ICV_IGRPEN1_EL1 handler

Add a handler for reading/writing the guest's view of the ICC_IGRPEN1_EL1
register, which is located in the ICH_VMCR_EL2.VENG1 field.

Tested-by: Alexander Graf <agraf@suse.de>
Acked-by: David Daney <david.daney@cavium.com>
Reviewed-by: Eric Auger <eric.auger@redhat.com>
Reviewed-by: Christoffer Dall <cdall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <cdall@linaro.org>

diff --git a/virt/kvm/arm/hyp/vgic-v3-sr.c b/virt/kvm/arm/hyp/vgic-v3-sr.c
index fe021abc8b5149cfc4da193d63b7090853fa00b5..25f09721241f4dd4f08b6c53c59e8287fa861b31 100644 (file)
--- a/virt/kvm/arm/hyp/vgic-v3-sr.c
+++ b/virt/kvm/arm/hyp/vgic-v3-sr.c
@@ -401,6 +401,23 @@ static unsigned int __hyp_text __vgic_v3_get_bpr1(u32 vmcr)
        return bpr;
 }
 
+static void __hyp_text __vgic_v3_read_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       vcpu_set_reg(vcpu, rt, !!(vmcr & ICH_VMCR_ENG1_MASK));
+}
+
+static void __hyp_text __vgic_v3_write_igrpen1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
+{
+       u64 val = vcpu_get_reg(vcpu, rt);
+
+       if (val & 1)
+               vmcr |= ICH_VMCR_ENG1_MASK;
+       else
+               vmcr &= ~ICH_VMCR_ENG1_MASK;
+
+       __vgic_v3_write_vmcr(vmcr);
+}
+
 static void __hyp_text __vgic_v3_read_bpr1(struct kvm_vcpu *vcpu, u32 vmcr, int rt)
 {
        vcpu_set_reg(vcpu, rt, __vgic_v3_get_bpr1(vmcr));
@@ -448,6 +465,12 @@ int __hyp_text __vgic_v3_perform_cpuif_access(struct kvm_vcpu *vcpu)
        is_read = (esr & ESR_ELx_SYS64_ISS_DIR_MASK) == ESR_ELx_SYS64_ISS_DIR_READ;
 
        switch (sysreg) {
+       case SYS_ICC_GRPEN1_EL1:
+               if (is_read)
+                       fn = __vgic_v3_read_igrpen1;
+               else
+                       fn = __vgic_v3_write_igrpen1;
+               break;
        case SYS_ICC_BPR1_EL1:
                if (is_read)
                        fn = __vgic_v3_read_bpr1;