Add programming of GDFIFOCFG register in device mode.
It must contain start address for EP Info block and
total FIFO depth.
Signed-off-by: Sevak Arakelyan <sevaka@synopsys.com>
Signed-off-by: John Youn <johnyoun@synopsys.com>
Signed-off-by: Felipe Balbi <felipe.balbi@linux.intel.com>
val = dwc2_readl(hsotg->regs + DPTXFSIZN(ep));
}
+ dwc2_writel(hsotg->hw_params.total_fifo_size |
+ addr << GDFIFOCFG_EPINFOBASE_SHIFT,
+ hsotg->regs + GDFIFOCFG);
/*
* according to p428 of the design guide, we need to ensure that
* all fifos are flushed before continuing