drm/nvc0: fix suspend/resume of PGRAPH/PCOPYn

We need the physical VRAM address in vinst, even for objects mapped into
a vm, as the gpuobj suspend/resume code uses PMEM to access the object.

Previously, vinst was overloaded to mean "VRAM address" for !VM objects,
and "VM address" for VM objects, causing the wrong data to be accessed
during suspend/resume.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>

diff --git a/drivers/gpu/drm/nouveau/nouveau_drv.h b/drivers/gpu/drm/nouveau/nouveau_drv.h
index 276fac7b7569607e50a6feda69369167f99e837a..7136ad34921d262aab4936df70a539d7b3a643b5 100644 (file)
--- a/drivers/gpu/drm/nouveau/nouveau_drv.h
+++ b/drivers/gpu/drm/nouveau/nouveau_drv.h
@@ -176,9 +176,10 @@ struct nouveau_gpuobj {
        uint32_t flags;
 
        u32 size;
-       u32 pinst;
-       u32 cinst;
-       u64 vinst;
+       u32 pinst;      /* PRAMIN BAR offset */
+       u32 cinst;      /* Channel offset */
+       u64 vinst;      /* VRAM address */
+       u64 linst;      /* VM address */
 
        uint32_t engine;
        uint32_t class;

diff --git a/drivers/gpu/drm/nouveau/nv50_instmem.c b/drivers/gpu/drm/nouveau/nv50_instmem.c
index 4f95a1e5822e151ab89fcc51ba665c47cc4b50e4..ccea671346c9761c67862514c6e69d916d1e2892 100644 (file)
--- a/drivers/gpu/drm/nouveau/nv50_instmem.c
+++ b/drivers/gpu/drm/nouveau/nv50_instmem.c
@@ -305,7 +305,6 @@ struct nv50_gpuobj_node {
        u32 align;
 };
 
-
 int
 nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
 {
@@ -345,7 +344,7 @@ nv50_instmem_get(struct nouveau_gpuobj *gpuobj, u32 size, u32 align)
                }
 
                nouveau_vm_map(&node->chan_vma, node->vram);
-               gpuobj->vinst = node->chan_vma.offset;
+               gpuobj->linst = node->chan_vma.offset;
        }
 
        gpuobj->size = size;

diff --git a/drivers/gpu/drm/nouveau/nvc0_copy.c b/drivers/gpu/drm/nouveau/nvc0_copy.c
index 208fa7ab3f42ebb28176d14ba8e95a45e90bf55c..02c00bbeb9e5b1d3b51a7687ba6859937765bd57 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_copy.c
+++ b/drivers/gpu/drm/nouveau/nvc0_copy.c
@@ -54,8 +54,8 @@ nvc0_copy_context_new(struct nouveau_channel *chan, int engine)
        if (ret)
                return ret;
 
-       nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->vinst));
-       nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->vinst));
+       nv_wo32(ramin, pcopy->ctx + 0, lower_32_bits(ctx->linst));
+       nv_wo32(ramin, pcopy->ctx + 4, upper_32_bits(ctx->linst));
        dev_priv->engine.instmem.flush(dev);
 
        chan->engctx[engine] = ctx;

diff --git a/drivers/gpu/drm/nouveau/nvc0_graph.c b/drivers/gpu/drm/nouveau/nvc0_graph.c
index c99b3caa568cdbce74ae2ba25622df89cafc4eb6..6c06d6636a3ca2e289b426f3c4a669c44ad3407e 100644 (file)
--- a/drivers/gpu/drm/nouveau/nvc0_graph.c
+++ b/drivers/gpu/drm/nouveau/nvc0_graph.c
@@ -131,27 +131,27 @@ nvc0_graph_create_context_mmio_list(struct nouveau_channel *chan)
 
 
        nv_wo32(grch->mmio, i++ * 4, 0x00408004);
-       nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
+       nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
        nv_wo32(grch->mmio, i++ * 4, 0x00408008);
        nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 
        nv_wo32(grch->mmio, i++ * 4, 0x0040800c);
-       nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
+       nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
        nv_wo32(grch->mmio, i++ * 4, 0x00408010);
        nv_wo32(grch->mmio, i++ * 4, 0x80000000);
 
        nv_wo32(grch->mmio, i++ * 4, 0x00418810);
-       nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->vinst >> 12);
+       nv_wo32(grch->mmio, i++ * 4, 0x80000000 | grch->unk418810->linst >> 12);
        nv_wo32(grch->mmio, i++ * 4, 0x00419848);
-       nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->vinst >> 12);
+       nv_wo32(grch->mmio, i++ * 4, 0x10000000 | grch->unk418810->linst >> 12);
 
        nv_wo32(grch->mmio, i++ * 4, 0x00419004);
-       nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->vinst >> 8);
+       nv_wo32(grch->mmio, i++ * 4, grch->unk40800c->linst >> 8);
        nv_wo32(grch->mmio, i++ * 4, 0x00419008);
        nv_wo32(grch->mmio, i++ * 4, 0x00000000);
 
        nv_wo32(grch->mmio, i++ * 4, 0x00418808);
-       nv_wo32(grch->mmio, i++ * 4, grch->unk408004->vinst >> 8);
+       nv_wo32(grch->mmio, i++ * 4, grch->unk408004->linst >> 8);
        nv_wo32(grch->mmio, i++ * 4, 0x0041880c);
        nv_wo32(grch->mmio, i++ * 4, 0x80000018);
 
@@ -197,8 +197,8 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
        if (ret)
                goto error;
 
-       nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->vinst) | 4);
-       nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->vinst));
+       nv_wo32(chan->ramin, 0x0210, lower_32_bits(grctx->linst) | 4);
+       nv_wo32(chan->ramin, 0x0214, upper_32_bits(grctx->linst));
        pinstmem->flush(dev);
 
        if (!priv->grctx_vals) {
@@ -213,8 +213,8 @@ nvc0_graph_context_new(struct nouveau_channel *chan, int engine)
        nv_wo32(grctx, 0xf4, 0);
        nv_wo32(grctx, 0xf8, 0);
        nv_wo32(grctx, 0x10, grch->mmio_nr);
-       nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->vinst));
-       nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->vinst));
+       nv_wo32(grctx, 0x14, lower_32_bits(grch->mmio->linst));
+       nv_wo32(grctx, 0x18, upper_32_bits(grch->mmio->linst));
        nv_wo32(grctx, 0x1c, 1);
        nv_wo32(grctx, 0x20, 0);
        nv_wo32(grctx, 0x28, 0);