perf/x86/amd: Add support for new IOMMU performance events
authorSuravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>
Mon, 29 Feb 2016 04:23:29 +0000 (22:23 -0600)
committerIngo Molnar <mingo@kernel.org>
Mon, 21 Mar 2016 08:35:28 +0000 (09:35 +0100)
This patch adds new IOMMU performance event based on
the information in table 74 of the AMD I/O Virtualization Technology
(IOMMU) Specification (Document Id: 4882, Rev 2.62, Feb 2015)

Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Joerg Roedel <jroedel@suse.de>
Acked-by: Joerg Roedel <jroedel@suse.de>
Cc: <acme@kernel.org>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: David Ahern <dsahern@gmail.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Link: http://support.amd.com/TechDocs/48882_IOMMU.pdf
Signed-off-by: Ingo Molnar <mingo@kernel.org>
arch/x86/events/amd/iommu.c

index 635e5eba0caf87f432d97bcf178db025e5cb4cca..40625ca7a190953fc87c386a03017bab96903435 100644 (file)
@@ -118,6 +118,11 @@ static struct amd_iommu_event_desc amd_iommu_v2_event_descs[] = {
        AMD_IOMMU_EVENT_DESC(cmd_processed,           "csource=0x11"),
        AMD_IOMMU_EVENT_DESC(cmd_processed_inv,       "csource=0x12"),
        AMD_IOMMU_EVENT_DESC(tlb_inv,                 "csource=0x13"),
+       AMD_IOMMU_EVENT_DESC(ign_rd_wr_mmio_1ff8h,    "csource=0x14"),
+       AMD_IOMMU_EVENT_DESC(vapic_int_non_guest,     "csource=0x15"),
+       AMD_IOMMU_EVENT_DESC(vapic_int_guest,         "csource=0x16"),
+       AMD_IOMMU_EVENT_DESC(smi_recv,                "csource=0x17"),
+       AMD_IOMMU_EVENT_DESC(smi_blk,                 "csource=0x18"),
        { /* end: all zeroes */ },
 };