projects / GitHub / moto-9609 / android_kernel_motorola_exynos9610.git / commitdiff
? search:
summary | shortlog | log | commit | commitdiff | tree
raw | patch | inline | side by side (parent: 085eefb)
[ARM] 5318/1: Swap the PRRR and NMRR values in proc-v7.S
authorCatalin Marinas <catalin.marinas@arm.com>
Wed, 22 Oct 2008 12:04:30 +0000 (13:04 +0100)
committerRussell King <rmk+kernel@arm.linux.org.uk>
Wed, 22 Oct 2008 18:40:21 +0000 (19:40 +0100)
A typo caused these values to be swapped leading to incorrect memory
type attributes.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
arch/arm/mm/proc-v7.S patch | blob | blame | history

diff --git a/arch/arm/mm/proc-v7.S b/arch/arm/mm/proc-v7.S
index 34e424041927fe57f464fa4612cd5e99b0c1ebe9..07f82db70945f7d3582dcd6c9f589ebcce648af9 100644 (file)
--- a/arch/arm/mm/proc-v7.S
+++ b/arch/arm/mm/proc-v7.S
@@ -180,8 +180,8 @@ __v7_setup:
        mov     r10, #0x1f                      @ domains 0, 1 = manager
        mcr     p15, 0, r10, c3, c0, 0          @ load domain access register
 #endif
-       ldr     r5, =0x40e040e0
-       ldr     r6, =0xff0aa1a8
+       ldr     r5, =0xff0aa1a8
+       ldr     r6, =0x40e040e0
        mcr     p15, 0, r5, c10, c2, 0          @ write PRRR
        mcr     p15, 0, r6, c10, c2, 1          @ write NMRR
        adr     r5, v7_crval