MIPS: ptrace: Fix PTRACE_PEEKUSR requests for 64-bit FGRs
authorMaciej W. Rozycki <macro@mips.com>
Wed, 16 May 2018 15:39:58 +0000 (16:39 +0100)
committerGreg Kroah-Hartman <gregkh@linuxfoundation.org>
Tue, 5 Jun 2018 09:41:58 +0000 (11:41 +0200)
commit c7e814628df65f424fe197dde73bfc67e4a244d7 upstream.

Use 64-bit accesses for 64-bit floating-point general registers with
PTRACE_PEEKUSR, removing the truncation of their upper halves in the
FR=1 mode, caused by commit bbd426f542cb ("MIPS: Simplify FP context
access"), which inadvertently switched them to using 32-bit accesses.

The PTRACE_POKEUSR side is fine as it's never been broken and continues
using 64-bit accesses.

Fixes: bbd426f542cb ("MIPS: Simplify FP context access")
Signed-off-by: Maciej W. Rozycki <macro@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: linux-mips@linux-mips.org
Cc: <stable@vger.kernel.org> # 3.15+
Patchwork: https://patchwork.linux-mips.org/patch/19334/
Signed-off-by: James Hogan <jhogan@kernel.org>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
arch/mips/kernel/ptrace.c
arch/mips/kernel/ptrace32.c

index 006105fb12fef2ba1859ee5f323f0e2aca051258..e058cd300713d19bf656bc243f3f6cec9728a962 100644 (file)
@@ -809,7 +809,7 @@ long arch_ptrace(struct task_struct *child, long request,
                                break;
                        }
 #endif
-                       tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
+                       tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
                        break;
                case PC:
                        tmp = regs->cp0_epc;
index 4a157d3249acd5cf29e6bca89df9f4c984137cd4..89026d33a07bf7027400e56fa49fcb65da21ea60 100644 (file)
@@ -108,7 +108,7 @@ long compat_arch_ptrace(struct task_struct *child, compat_long_t request,
                                                addr & 1);
                                break;
                        }
-                       tmp = get_fpr32(&fregs[addr - FPR_BASE], 0);
+                       tmp = get_fpr64(&fregs[addr - FPR_BASE], 0);
                        break;
                case PC:
                        tmp = regs->cp0_epc;