drm/radeon: halt engines before disabling MC (si)

It's better to halt the engines before we disable the MC.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c
index 7a8ca728f36fd38436e9c4bbfae9294a54902309..89b564ec3d3440eb3d53e06b1d07393d9b548393 100644 (file)
--- a/drivers/gpu/drm/radeon/si.c
+++ b/drivers/gpu/drm/radeon/si.c
@@ -2220,11 +2220,6 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
        dev_info(rdev->dev, "  VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x%08X\n",
                 RREG32(VM_CONTEXT1_PROTECTION_FAULT_STATUS));
 
-       evergreen_mc_stop(rdev, &save);
-       if (evergreen_mc_wait_for_idle(rdev)) {
-               dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
-       }
-
        /* Disable CP parsing/prefetching */
        WREG32(CP_ME_CNTL, CP_ME_HALT | CP_PFP_HALT | CP_CE_HALT);
 
@@ -2241,6 +2236,13 @@ static void si_gpu_soft_reset(struct radeon_device *rdev, u32 reset_mask)
                WREG32(DMA_RB_CNTL + DMA1_REGISTER_OFFSET, tmp);
        }
 
+       udelay(50);
+
+       evergreen_mc_stop(rdev, &save);
+       if (evergreen_mc_wait_for_idle(rdev)) {
+               dev_warn(rdev->dev, "Wait for MC idle timedout !\n");
+       }
+
        if (reset_mask & (RADEON_RESET_GFX | RADEON_RESET_COMPUTE | RADEON_RESET_CP)) {
                grbm_soft_reset = SOFT_RESET_CB |
                        SOFT_RESET_DB |