hisi_sas: for v2 hw only set ITCT qw2 for SAS device
authorJohn Garry <john.garry@huawei.com>
Fri, 8 Apr 2016 09:23:14 +0000 (17:23 +0800)
committerMartin K. Petersen <martin.petersen@oracle.com>
Fri, 15 Apr 2016 20:53:17 +0000 (16:53 -0400)
This patch fixes the ITCT table setup as it should be configured
differently for SAS and SATA devices.  For SATA disks there is no need
to set qw2 (already zeroed).  Also, link parameters for Bus inactive
limit, max connection time limit, and reject to open limit timers
parameters are changed to match global config register,
MAX_CON_TIME_LIMIT_TIME, as recommended by hw team.

Signed-off-by: John Garry <john.garry@huawei.com>
Reviewed-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Martin K. Petersen <martin.petersen@oracle.com>
drivers/scsi/hisi_sas/hisi_sas_v2_hw.c

index cc083b9b1041a1522560011678568e4b0348306b..4276594a14c8d186aa9c16dfd787f42c8fe449cd 100644 (file)
@@ -554,10 +554,11 @@ static void setup_itct_v2_hw(struct hisi_hba *hisi_hba,
        itct->sas_addr = __swab64(itct->sas_addr);
 
        /* qw2 */
-       itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
-                               (0xff00ULL << ITCT_HDR_BITLT_OFF) |
-                               (0xff00ULL << ITCT_HDR_MCTLT_OFF) |
-                               (0xff00ULL << ITCT_HDR_RTOLT_OFF));
+       if (!dev_is_sata(device))
+               itct->qw2 = cpu_to_le64((500ULL << ITCT_HDR_INLT_OFF) |
+                                       (0x1ULL << ITCT_HDR_BITLT_OFF) |
+                                       (0x32ULL << ITCT_HDR_MCTLT_OFF) |
+                                       (0x1ULL << ITCT_HDR_RTOLT_OFF));
 }
 
 static void free_device_v2_hw(struct hisi_hba *hisi_hba,
@@ -715,7 +716,7 @@ static void init_reg_v2_hw(struct hisi_hba *hisi_hba)
        hisi_sas_write32(hisi_hba, HGC_SAS_TX_OPEN_FAIL_RETRY_CTRL, 0x7FF);
        hisi_sas_write32(hisi_hba, OPENA_WT_CONTI_TIME, 0x1);
        hisi_sas_write32(hisi_hba, I_T_NEXUS_LOSS_TIME, 0x1F4);
-       hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x4E20);
+       hisi_sas_write32(hisi_hba, MAX_CON_TIME_LIMIT_TIME, 0x32);
        hisi_sas_write32(hisi_hba, BUS_INACTIVE_LIMIT_TIME, 0x1);
        hisi_sas_write32(hisi_hba, CFG_AGING_TIME, 0x1);
        hisi_sas_write32(hisi_hba, HGC_ERR_STAT_EN, 0x1);