drm/amdgpu: add uvd enc rings
authorLeo Liu <leo.liu@amd.com>
Tue, 10 Jan 2017 16:23:23 +0000 (11:23 -0500)
committerAlex Deucher <alexander.deucher@amd.com>
Thu, 30 Mar 2017 03:53:45 +0000 (23:53 -0400)
And initialize them

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drivers/gpu/drm/amd/amdgpu/amdgpu_ring.h
drivers/gpu/drm/amd/amdgpu/amdgpu_uvd.h

index f0c1a6bbd4440770b498f8a0b19cfdc3d2d27214..1508c08759dc75d54cc20ed852c9e6ad8f983b3f 100644 (file)
 #include "gpu_scheduler.h"
 
 /* max number of rings */
-#define AMDGPU_MAX_RINGS               16
+#define AMDGPU_MAX_RINGS               18
 #define AMDGPU_MAX_GFX_RINGS           1
 #define AMDGPU_MAX_COMPUTE_RINGS       8
 #define AMDGPU_MAX_VCE_RINGS           3
+#define AMDGPU_MAX_UVD_ENC_RINGS       2
 
 /* some special values for the owner field */
 #define AMDGPU_FENCE_OWNER_UNDEFINED   ((void*)0ul)
index 797210dd52deceb71471c598566be29c9be33d79..7b7f468978111752fb76a4001895e97ff9958644 100644 (file)
@@ -43,11 +43,13 @@ struct amdgpu_uvd {
        struct delayed_work     idle_work;
        const struct firmware   *fw;    /* UVD firmware */
        struct amdgpu_ring      ring;
+       struct amdgpu_ring      ring_enc[AMDGPU_MAX_UVD_ENC_RINGS];
        struct amdgpu_irq_src   irq;
        bool                    address_64_bit;
        bool                    use_ctx_buf;
        struct amd_sched_entity entity;
        uint32_t                srbm_soft_reset;
+       unsigned                num_enc_rings;
 };
 
 int amdgpu_uvd_sw_init(struct amdgpu_device *adev);