ARC: [plat-axs103] use clk driver #2: Add core pll node to DT to manage cpu clk

Add core pll node (core_clk) to manage cpu frequency.
core_clk represents pll itself.
input_clk represents clock signal source (basically xtal) which
comes to pll input.

Signed-off-by: Eugeniy Paltsev <Eugeniy.Paltsev@synopsys.com>
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>

diff --git a/arch/arc/boot/dts/axc003.dtsi b/arch/arc/boot/dts/axc003.dtsi
index cc9239ef8d08c9f6efbe6dbee0323f283c4f5e37..dca7e39409beb7b9a472365022b61e6a3f46ad87 100644 (file)
--- a/arch/arc/boot/dts/axc003.dtsi
+++ b/arch/arc/boot/dts/axc003.dtsi
@@ -24,10 +24,17 @@
 
                ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
 
-               core_clk: core_clk {
+               input_clk: input-clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                       clock-frequency = <90000000>;
+                       clock-frequency = <33333333>;
+               };
+
+               core_clk: core-clk@80 {
+                       compatible = "snps,axs10x-arc-pll-clock";
+                       reg = <0x80 0x10>, <0x100 0x10>;
+                       #clock-cells = <0>;
+                       clocks = <&input_clk>;
                };
 
                core_intc: archs-intc@cpu {

diff --git a/arch/arc/boot/dts/axc003_idu.dtsi b/arch/arc/boot/dts/axc003_idu.dtsi
index 4ebb2170abecc7e00cd581a7ca6dcef6e94231e0..5b56beffc1c5137b402d7db4d85db979e4ea3eef 100644 (file)
--- a/arch/arc/boot/dts/axc003_idu.dtsi
+++ b/arch/arc/boot/dts/axc003_idu.dtsi
@@ -24,10 +24,17 @@
 
                ranges = <0x00000000 0x0 0xf0000000 0x10000000>;
 
-               core_clk: core_clk {
+               input_clk: input-clk {
                        #clock-cells = <0>;
                        compatible = "fixed-clock";
-                       clock-frequency = <100000000>;
+                       clock-frequency = <33333333>;
+               };
+
+               core_clk: core-clk@80 {
+                       compatible = "snps,axs10x-arc-pll-clock";
+                       reg = <0x80 0x10>, <0x100 0x10>;
+                       #clock-cells = <0>;
+                       clocks = <&input_clk>;
                };
 
                core_intc: archs-intc@cpu {