dma_alloc_noncoherent()).
int
-dma_is_consistent(dma_addr_t dma_handle)
+dma_is_consistent(struct device *dev, dma_addr_t dma_handle)
-returns true if the memory pointed to by the dma_handle is actually
-consistent.
+returns true if the device dev is performing consistent DMA on the memory
+area pointed to by the dma_handle.
int
dma_get_cache_alignment(void)
EXPORT_SYMBOL(dma_supported);
-int dma_is_consistent(dma_addr_t dma_addr)
+int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 1;
}
EXPORT_SYMBOL(dma_supported);
-int dma_is_consistent(dma_addr_t dma_addr)
+int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 1;
}
EXPORT_SYMBOL(dma_supported);
-int dma_is_consistent(dma_addr_t dma_addr)
+int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 1;
}
EXPORT_SYMBOL(dma_supported);
-int dma_is_consistent(dma_addr_t dma_addr)
+int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 1;
}
hostdata->status = memory + STATUS_OFFSET;
/* all of these offsets are L1_CACHE_BYTES separated. It is fatal
* if this isn't sufficient separation to avoid dma flushing issues */
- BUG_ON(!dma_is_consistent(pScript) && L1_CACHE_BYTES < dma_get_cache_alignment());
+ BUG_ON(!dma_is_consistent(hostdata->dev, pScript) && L1_CACHE_BYTES < dma_get_cache_alignment());
hostdata->slots = (struct NCR_700_command_slot *)(memory + SLOTS_OFFSET);
hostdata->dev = dev;
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(dev) (1)
+#define dma_is_consistent(d, h) (1)
int dma_set_mask(struct device *dev, u64 mask);
return 32;
}
-static inline int dma_is_consistent(dma_addr_t handle)
+static inline int dma_is_consistent(struct device *dev, dma_addr_t handle)
{
return !!arch_is_coherent();
}
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-static inline int dma_is_consistent(dma_addr_t dma_addr)
+static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 1;
}
return (1 << INTERNODE_CACHE_SHIFT);
}
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
static inline void
dma_cache_sync(void *vaddr, size_t size,
return 1 << L1_CACHE_SHIFT;
}
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
static inline
void dma_cache_sync(void *vaddr, size_t size,
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
static inline int
dma_get_cache_alignment(void)
return (1 << INTERNODE_CACHE_SHIFT);
}
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
static inline void
dma_cache_sync(void *vaddr, size_t size,
mb();
}
-#define dma_is_consistent(dma_handle) (1) /* all we do is coherent memory... */
+#define dma_is_consistent(d, h) (1) /* all we do is coherent memory... */
#endif /* _ASM_IA64_DMA_MAPPING_H */
return 1 << L1_CACHE_SHIFT;
}
-static inline int dma_is_consistent(dma_addr_t dma_addr)
+static inline int dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return 0;
}
return 128;
}
-extern int dma_is_consistent(dma_addr_t dma_addr);
+extern int dma_is_consistent(struct device *dev, dma_addr_t dma_addr);
extern void dma_cache_sync(void *vaddr, size_t size,
enum dma_data_direction direction);
}
static inline int
-dma_is_consistent(dma_addr_t dma_addr)
+dma_is_consistent(struct device *dev, dma_addr_t dma_addr)
{
return (hppa_dma_ops->dma_sync_single_for_cpu == NULL);
}
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
#ifdef CONFIG_NOT_COHERENT_CACHE
-#define dma_is_consistent(d) (0)
+#define dma_is_consistent(d, h) (0)
#else
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
#endif
static inline int dma_get_cache_alignment(void)
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
static inline int
dma_get_cache_alignment(void)
#define dma_alloc_noncoherent(d, s, h, f) dma_alloc_coherent(d, s, h, f)
#define dma_free_noncoherent(d, s, v, h) dma_free_coherent(d, s, v, h)
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
static inline int
dma_get_cache_alignment(void)
return boot_cpu_data.x86_clflush_size;
}
-#define dma_is_consistent(h) 1
+#define dma_is_consistent(d, h) 1
extern int dma_set_mask(struct device *dev, u64 mask);
return L1_CACHE_BYTES;
}
-#define dma_is_consistent(d) (1)
+#define dma_is_consistent(d, h) (1)
static inline void
dma_cache_sync(void *vaddr, size_t size,