iwlwifi: add support of FPGA fw
authorTzipi Peres <tzipi.peres@intel.com>
Wed, 14 Jun 2017 07:02:47 +0000 (10:02 +0300)
committerLuca Coelho <luciano.coelho@intel.com>
Wed, 9 Aug 2017 06:35:14 +0000 (09:35 +0300)
Load FW according to NIC type,
taking into account simulation, if exists.
This is determined by a prph register.

Signed-off-by: Tzipi Peres <tzipi.peres@intel.com>
Signed-off-by: Luca Coelho <luciano.coelho@intel.com>
drivers/net/wireless/intel/iwlwifi/cfg/a000.c
drivers/net/wireless/intel/iwlwifi/iwl-config.h
drivers/net/wireless/intel/iwlwifi/iwl-prph.h
drivers/net/wireless/intel/iwlwifi/pcie/trans.c

index 98f24cd1b44f17ee5253d8c7ce7641541bf19681..40d67a5a26354704ab67c12bf6ff174a84ed0879 100644 (file)
 #define IWL_A000_JF_FW_PRE     "iwlwifi-Qu-a0-jf-b0-"
 #define IWL_A000_HR_FW_PRE     "iwlwifi-Qu-a0-hr-a0-"
 #define IWL_A000_HR_CDB_FW_PRE "iwlwifi-QuIcp-z0-hrcdb-a0-"
+#define IWL_A000_HR_F0_FW_PRE  "iwlwifi-QuQnj-f0-hr-a0-"
 
 #define IWL_A000_HR_MODULE_FIRMWARE(api) \
        IWL_A000_HR_FW_PRE "-" __stringify(api) ".ucode"
 #define IWL_A000_JF_MODULE_FIRMWARE(api) \
        IWL_A000_JF_FW_PRE "-" __stringify(api) ".ucode"
+#define IWL_A000_HR_QNJ_MODULE_FIRMWARE(api) \
+       IWL_A000_HR_F0_FW_PRE "-" __stringify(api) ".ucode"
 
 #define NVM_HW_SECTION_NUM_FAMILY_A000         10
 
@@ -168,5 +171,16 @@ const struct iwl_cfg iwla000_2ax_cfg_hr = {
                .max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
 };
 
+const struct iwl_cfg iwla000_2ax_cfg_qnj_hr = {
+               .name = "Intel(R) Dual Band Wireless AX a000",
+               .fw_name_pre = IWL_A000_HR_F0_FW_PRE,
+               IWL_DEVICE_A000,
+               .ht_params = &iwl_a000_ht_params,
+               .nvm_ver = IWL_A000_NVM_VERSION,
+               .nvm_calib_ver = IWL_A000_TX_POWER_VERSION,
+               .max_ht_ampdu_exponent = IEEE80211_HT_MAX_AMPDU_64K,
+};
+
 MODULE_FIRMWARE(IWL_A000_HR_MODULE_FIRMWARE(IWL_A000_UCODE_API_MAX));
 MODULE_FIRMWARE(IWL_A000_JF_MODULE_FIRMWARE(IWL_A000_UCODE_API_MAX));
+MODULE_FIRMWARE(IWL_A000_HR_QNJ_MODULE_FIRMWARE(IWL_A000_UCODE_API_MAX));
index c52623cb7c2a1bc89d635f4406df70bc3101f340..573dbeed3fbf90236adf0b10b3a74cacb901c929 100644 (file)
@@ -463,6 +463,7 @@ extern const struct iwl_cfg iwla000_2ac_cfg_hr;
 extern const struct iwl_cfg iwla000_2ac_cfg_hr_cdb;
 extern const struct iwl_cfg iwla000_2ac_cfg_jf;
 extern const struct iwl_cfg iwla000_2ax_cfg_hr;
+extern const struct iwl_cfg iwla000_2ax_cfg_qnj_hr;
 #endif /* CONFIG_IWLMVM */
 
 #endif /* __IWL_CONFIG_H__ */
index 6772c59b7764a90f2e4c93c9b52f72a616d7bf61..fbce97ed4ecd02c6cf9d17b5ac42728e2a509a20 100644 (file)
@@ -404,6 +404,12 @@ enum aux_misc_master1_en {
 #define SB_CPU_2_STATUS                        0xA01E34
 #define UMAG_SB_CPU_1_STATUS           0xA038C0
 #define UMAG_SB_CPU_2_STATUS           0xA038C4
+#define UMAG_GEN_HW_STATUS             0xA038C8
+
+/* For UMAG_GEN_HW_STATUS reg check */
+enum {
+       UMAG_GEN_HW_IS_FPGA = BIT(1),
+};
 
 /* FW chicken bits */
 #define LMPM_CHICK                     0xA01FF8
index 32f06f14328c9b44bbadd04693f3c4e6b2d8fa67..439cf424e058d22c7c37c109faa6a5651045132b 100644 (file)
@@ -3137,7 +3137,18 @@ struct iwl_trans *iwl_trans_pcie_alloc(struct pci_dev *pdev,
                iwl_set_bit(trans, CSR_HOST_CHICKEN,
                            CSR_HOST_CHICKEN_PM_IDLE_SRC_DIS_SB_PME);
 
+#if IS_ENABLED(CONFIG_IWLMVM)
        trans->hw_rf_id = iwl_read32(trans, CSR_HW_RF_ID);
+       if (trans->hw_rf_id == CSR_HW_RF_ID_TYPE_HR) {
+               u32 hw_status;
+
+               hw_status = iwl_read_prph(trans, UMAG_GEN_HW_STATUS);
+               if (hw_status & UMAG_GEN_HW_IS_FPGA)
+                       trans->cfg = &iwla000_2ax_cfg_qnj_hr;
+               else
+                       trans->cfg = &iwla000_2ac_cfg_hr;
+       }
+#endif
 
        iwl_pcie_set_interrupt_capa(pdev, trans);
        trans->hw_id = (pdev->device << 16) + pdev->subsystem_device;