clk: ux500: fix erroneous bit assignment
authorLinus Walleij <linus.walleij@linaro.org>
Fri, 18 Oct 2013 08:56:14 +0000 (10:56 +0200)
committerLinus Walleij <linus.walleij@linaro.org>
Fri, 18 Oct 2013 11:25:28 +0000 (13:25 +0200)
Due to a typo or similar, the peripheral group 2 clock 11
gate was set to bit 1 instead of bit 11. We need to fix this
to be able to set the correct enable bit in the device tree:
when trying to correct the bit assignment in the device tree,
the system would hang.

Cc: Mike Turquette <mturquette@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
drivers/clk/ux500/u8500_of_clk.c

index b768b507c95c8c200b1a8b07e6718708d771948b..cdeff299de26d3a78320022b3473c484bbb78faf 100644 (file)
@@ -339,7 +339,7 @@ void u8500_of_clk_init(u32 clkrst1_base, u32 clkrst2_base, u32 clkrst3_base,
 
        clk = clk_reg_prcc_pclk("p2_pclk11", "per2clk", clkrst2_base,
                                BIT(11), 0);
-       PRCC_PCLK_STORE(clk, 2, 1);
+       PRCC_PCLK_STORE(clk, 2, 11);
 
        clk = clk_reg_prcc_pclk("p2_pclk12", "per2clk", clkrst2_base,
                                BIT(12), 0);