arm64: dts: juno: add cpu capacity-dmips-mhz information to R1 boards

This patch adds cpu capacity-dmips-mhz information to Juno R1 boards.

Cc: Rob Herring <robh+dt@kernel.org>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Kumar Gala <galak@codeaurora.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Liviu Dudau <Liviu.Dudau@arm.com>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Jon Medhurst <tixy@linaro.org>
Cc: Olof Johansson <olof@lixom.net>
Cc: Robin Murphy <robin.murphy@arm.com>
Cc: devicetree@vger.kernel.org
Signed-off-by: Juri Lelli <juri.lelli@arm.com>
[sudeep.holla@arm.com: reformated subject and updated changelog]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>

diff --git a/arch/arm64/boot/dts/arm/juno-r1.dts b/arch/arm64/boot/dts/arm/juno-r1.dts
index 123a58b29cbdc13687f196339cc3d60c96512e8f..3be8a3ef671c02019d50a62fad6585166f0281d5 100644 (file)
--- a/arch/arm64/boot/dts/arm/juno-r1.dts
+++ b/arch/arm64/boot/dts/arm/juno-r1.dts
@@ -90,6 +90,7 @@
                        next-level-cache = <&A57_L2>;
                        clocks = <&scpi_dvfs 0>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <1024>;
                };
 
                A57_1: cpu@1 {
@@ -100,6 +101,7 @@
                        next-level-cache = <&A57_L2>;
                        clocks = <&scpi_dvfs 0>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <1024>;
                };
 
                A53_0: cpu@100 {
@@ -110,6 +112,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <578>;
                };
 
                A53_1: cpu@101 {
@@ -120,6 +123,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <578>;
                };
 
                A53_2: cpu@102 {
@@ -130,6 +134,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <578>;
                };
 
                A53_3: cpu@103 {
@@ -140,6 +145,7 @@
                        next-level-cache = <&A53_L2>;
                        clocks = <&scpi_dvfs 1>;
                        cpu-idle-states = <&CPU_SLEEP_0 &CLUSTER_SLEEP_0>;
+                       capacity-dmips-mhz = <578>;
                };
 
                A57_L2: l2-cache0 {