[COMMON] spi: s3c64xx: Fix div factor for USI v2.

This patch fixes SPI div factor from 2 to 4 due to HW change on USIv2
USIv2 has fixed 4 time divider so that SW needs to change requiring
4 time bigger source clock

Change-Id: I6387556ad7f493d5d0e4a699979fb868704fddd8
Signed-off-by: Kyungwoo Kang <kwoo.kang@samsung.com>

diff --git a/drivers/spi/spi-s3c64xx.c b/drivers/spi/spi-s3c64xx.c
index 6ce061d84fe9c6523d6d648a00343adbedeab991..dbadaa8a9c3575fed6ce57c641ce864e51498a16 100644 (file)
--- a/drivers/spi/spi-s3c64xx.c
+++ b/drivers/spi/spi-s3c64xx.c
@@ -790,8 +790,8 @@ static void s3c64xx_spi_config(struct s3c64xx_spi_driver_data *sdd)
        writel(val, regs + S3C64XX_SPI_MODE_CFG);
 
        if (sdd->port_conf->clk_from_cmu) {
-               /* There is half-multiplier before the SPI */
-               clk_set_rate(sdd->src_clk, sdd->cur_speed * 2);
+               /* There is a quarter-multiplier before the SPI */
+               clk_set_rate(sdd->src_clk, sdd->cur_speed * 4);
        } else {
                /* Configure Clock */
                val = readl(regs + S3C64XX_SPI_CLK_CFG);