powerpc/mm: Cleanup bits definition between hash and radix.
authorAneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Tue, 21 Mar 2017 17:29:53 +0000 (22:59 +0530)
committerMichael Ellerman <mpe@ellerman.id.au>
Fri, 31 Mar 2017 12:09:48 +0000 (23:09 +1100)
Define everything based on bits present in pgtable.h. This will help in easily
identifying overlapping bits between hash/radix.

No functional change with this patch.

Reviewed-by: Paul Mackerras <paulus@ozlabs.org>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
arch/powerpc/include/asm/book3s/64/hash-64k.h
arch/powerpc/include/asm/book3s/64/hash.h
arch/powerpc/include/asm/book3s/64/pgtable.h
arch/powerpc/include/asm/book3s/64/radix.h

index f3dd21efa2ead0e059fcfcca0056a20c22d56131..b39f0b86405e0737f6ddceb3d8492b164630d5bc 100644 (file)
@@ -6,6 +6,10 @@
 #define H_PUD_INDEX_SIZE  5
 #define H_PGD_INDEX_SIZE  12
 
+/*
+ * 64k aligned address free up few of the lower bits of RPN for us
+ * We steal that here. For more deatils look at pte_pfn/pfn_pte()
+ */
 #define H_PAGE_COMBO   0x00001000 /* this is a combo 4k page */
 #define H_PAGE_4K_PFN  0x00002000 /* PFN is for a single 4k page */
 /*
index f7b721bbf918bf055b5c5a0efa8cfc90de053384..ec2828b1db0712f5d9aee2b8f170f95293c479dd 100644 (file)
  * We could create separate kernel read-only if we used the 3 PP bits
  * combinations that newer processors provide but we currently don't.
  */
-#define H_PAGE_BUSY            0x00800 /* software: PTE & hash are busy */
+#define H_PAGE_BUSY            _RPAGE_SW1 /* software: PTE & hash are busy */
 #define H_PTE_NONE_MASK                _PAGE_HPTEFLAGS
 #define H_PAGE_F_GIX_SHIFT     57
-#define H_PAGE_F_GIX           (7ul << 57)     /* HPTE index within HPTEG */
-#define H_PAGE_F_SECOND                (1ul << 60)     /* HPTE is in 2ndary HPTEG */
-#define H_PAGE_HASHPTE         (1ul << 61)     /* PTE has associated HPTE */
+/* (7ul << 57) HPTE index within HPTEG */
+#define H_PAGE_F_GIX           (_RPAGE_RSV2 | _RPAGE_RSV3 | _RPAGE_RSV4)
+#define H_PAGE_F_SECOND                _RPAGE_RSV1     /* HPTE is in 2ndary HPTEG */
+#define H_PAGE_HASHPTE         _RPAGE_SW0      /* PTE has associated HPTE */
 
 #ifdef CONFIG_PPC_64K_PAGES
 #include <asm/book3s/64/hash-64k.h>
index 8f4d41936e5a90986c679876f66bfd15339de102..c39bc4cb92471e6953d05f961da59730f77443c4 100644 (file)
 #endif
 #define _PAGE_SPECIAL          _RPAGE_SW2 /* software: special page */
 
-/*
- * For P9 DD1 only, we need to track whether the pte's huge.
- */
-#define _PAGE_LARGE    _RPAGE_RSV1
-
-
-#define _PAGE_PTE              (1ul << 62)     /* distinguishes PTEs from pointers */
-#define _PAGE_PRESENT          (1ul << 63)     /* pte contains a translation */
+#define _PAGE_PTE              0x4000000000000000UL    /* distinguishes PTEs from pointers */
+#define _PAGE_PRESENT          0x8000000000000000UL    /* pte contains a translation */
 /*
  * Drivers request for cache inhibited pte mapping using _PAGE_NO_CACHE
  * Instead of fixing all of them, add an alternate define which
index 9e0bb7cd6e22ce7351579e8e61f1803db23a2e49..2a2ea47a9bd226aa593bd16c1e86e4e65a43ea4b 100644 (file)
 #include <asm/book3s/64/radix-4k.h>
 #endif
 
+/*
+ * For P9 DD1 only, we need to track whether the pte's huge.
+ */
+#define _PAGE_LARGE    _RPAGE_RSV1
+
+
 #ifndef __ASSEMBLY__
 #include <asm/book3s/64/tlbflush-radix.h>
 #include <asm/cpu_has_feature.h>