ar9462_common_rx_gain_table_2p0,
ARRAY_SIZE(ar9462_common_rx_gain_table_2p0), 2);
- INIT_INI_ARRAY(&ah->ini_BTCOEX_MAX_TXPWR,
- ar9462_2p0_BTCOEX_MAX_TXPWR_table,
- ARRAY_SIZE(ar9462_2p0_BTCOEX_MAX_TXPWR_table),
- 2);
-
/* Awake -> Sleep Setting */
INIT_INI_ARRAY(&ah->iniPcieSerdes,
PCIE_PLL_ON_CREQ_DIS_L1_2P0,
REG_WRITE_ARRAY(&ah->iniAdditional, 1, regWrites);
- if (AR_SREV_9462(ah))
- ar9003_hw_prog_ini(ah, &ah->ini_BTCOEX_MAX_TXPWR, 1);
-
if (chan->channel == 2484)
ar9003_hw_prog_ini(ah, &ah->ini_japan2484, 1);
{0x0000b1fc, 0x00000196},
};
-static const u32 ar9462_2p0_BTCOEX_MAX_TXPWR_table[][2] = {
- /* Addr allmodes */
- {0x000018c0, 0x10101010},
- {0x000018c4, 0x10101010},
- {0x000018c8, 0x10101010},
- {0x000018cc, 0x10101010},
- {0x000018d0, 0x10101010},
- {0x000018d4, 0x10101010},
- {0x000018d8, 0x10101010},
- {0x000018dc, 0x10101010},
-};
-
#endif /* INITVALS_9462_2P0_H */