powerpc: Routines for FP/VSX/VMX unavailable during a transaction

We do lazy FP but not lazy TM (ie. userspace starts with MSR TM=1 FP=0).  Hence
if userspace does an FP instruction during a transaction, we'll take an
fp unavailable exception.

This adds functions needed to handle this case.  We have to inject the current
FP state into the checkpoint so that the hardware can decide what to do with
the transaction.  We can't inject only the FP so we have to do a full treclaim
and recheckpoint to inject just the FP state.  This will cause the transaction
to be marked as aborted by the hardware.

This just add the routines needed to do this for FP, VMX and VSX.  It doesn't
hook them into the rest of the code yet.

Signed-off-by: Matt Evans <matt@ozlabs.org>
Signed-off-by: Michael Neuling <mikey@neuling.org>
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>

diff --git a/arch/powerpc/kernel/traps.c b/arch/powerpc/kernel/traps.c
index f829e05d8b1b68cda113718d7af62dfbaece9bf3..5c304697fe84d4e6731bd46f3131594f0c2f0628 100644 (file)
--- a/arch/powerpc/kernel/traps.c
+++ b/arch/powerpc/kernel/traps.c
@@ -58,6 +58,7 @@
 #include <asm/rio.h>
 #include <asm/fadump.h>
 #include <asm/switch_to.h>
+#include <asm/tm.h>
 #include <asm/debug.h>
 
 #if defined(CONFIG_DEBUGGER) || defined(CONFIG_KEXEC)
@@ -1189,6 +1190,88 @@ void tm_unavailable_exception(struct pt_regs *regs)
        die("Unexpected TM unavailable exception", regs, SIGABRT);
 }
 
+#ifdef CONFIG_PPC_TRANSACTIONAL_MEM
+
+extern void do_load_up_fpu(struct pt_regs *regs);
+
+void fp_unavailable_tm(struct pt_regs *regs)
+{
+       /* Note:  This does not handle any kind of FP laziness. */
+
+       TM_DEBUG("FP Unavailable trap whilst transactional at 0x%lx, MSR=%lx\n",
+                regs->nip, regs->msr);
+       tm_enable();
+
+        /* We can only have got here if the task started using FP after
+         * beginning the transaction.  So, the transactional regs are just a
+         * copy of the checkpointed ones.  But, we still need to recheckpoint
+         * as we're enabling FP for the process; it will return, abort the
+         * transaction, and probably retry but now with FP enabled.  So the
+         * checkpointed FP registers need to be loaded.
+        */
+       tm_reclaim(&current->thread, current->thread.regs->msr,
+                  TM_CAUSE_FAC_UNAV);
+       /* Reclaim didn't save out any FPRs to transact_fprs. */
+
+       /* Enable FP for the task: */
+       regs->msr |= (MSR_FP | current->thread.fpexc_mode);
+
+       /* This loads and recheckpoints the FP registers from
+        * thread.fpr[].  They will remain in registers after the
+        * checkpoint so we don't need to reload them after.
+        */
+       tm_recheckpoint(&current->thread, regs->msr);
+}
+
+#ifdef CONFIG_ALTIVEC
+extern void do_load_up_altivec(struct pt_regs *regs);
+
+void altivec_unavailable_tm(struct pt_regs *regs)
+{
+       /* See the comments in fp_unavailable_tm().  This function operates
+        * the same way.
+        */
+
+       TM_DEBUG("Vector Unavailable trap whilst transactional at 0x%lx,"
+                "MSR=%lx\n",
+                regs->nip, regs->msr);
+       tm_enable();
+       tm_reclaim(&current->thread, current->thread.regs->msr,
+                  TM_CAUSE_FAC_UNAV);
+       regs->msr |= MSR_VEC;
+       tm_recheckpoint(&current->thread, regs->msr);
+       current->thread.used_vr = 1;
+}
+#endif
+
+#ifdef CONFIG_VSX
+void vsx_unavailable_tm(struct pt_regs *regs)
+{
+       /* See the comments in fp_unavailable_tm().  This works similarly,
+        * though we're loading both FP and VEC registers in here.
+        *
+        * If FP isn't in use, load FP regs.  If VEC isn't in use, load VEC
+        * regs.  Either way, set MSR_VSX.
+        */
+
+       TM_DEBUG("VSX Unavailable trap whilst transactional at 0x%lx,"
+                "MSR=%lx\n",
+                regs->nip, regs->msr);
+
+       tm_enable();
+       /* This reclaims FP and/or VR regs if they're already enabled */
+       tm_reclaim(&current->thread, current->thread.regs->msr,
+                  TM_CAUSE_FAC_UNAV);
+
+       regs->msr |= MSR_VEC | MSR_FP | current->thread.fpexc_mode |
+               MSR_VSX;
+       /* This loads & recheckpoints FP and VRs. */
+       tm_recheckpoint(&current->thread, regs->msr);
+       current->thread.used_vsr = 1;
+}
+#endif
+#endif /* CONFIG_PPC_TRANSACTIONAL_MEM */
+
 void performance_monitor_exception(struct pt_regs *regs)
 {
        __get_cpu_var(irq_stat).pmu_irqs++;