dev_warn(chip->card->dev,
"No response from codec, disabling MSI: last cmd=0x%08x\n",
chip->last_cmd[addr]);
- free_irq(chip->irq, chip);
- chip->irq = -1;
- pci_disable_msi(chip->pci);
- chip->msi = 0;
- if (azx_acquire_irq(chip, 1) < 0) {
+ if (chip->ops->disable_msi_reset_irq &&
+ chip->ops->disable_msi_reset_irq(chip) < 0) {
bus->rirb_error = 1;
return -1;
}
return readb(addr);
}
+static int disable_msi_reset_irq(struct azx *chip)
+{
+ int err;
+
+ free_irq(chip->irq, chip);
+ chip->irq = -1;
+ pci_disable_msi(chip->pci);
+ chip->msi = 0;
+ err = azx_acquire_irq(chip, 1);
+ if (err < 0)
+ return err;
+
+ return 0;
+}
+
static const struct hda_controller_ops pci_hda_ops = {
.writel = pci_azx_writel,
.readl = pci_azx_readl,
.readw = pci_azx_readw,
.writeb = pci_azx_writeb,
.readb = pci_azx_readb,
+ .disable_msi_reset_irq = disable_msi_reset_irq,
};
static int azx_probe(struct pci_dev *pci,
u32 res[AZX_MAX_CODECS]; /* last read value */
};
+struct azx;
+
/* Functions to read/write to hda registers. */
struct hda_controller_ops {
/* Register Access */
u16 (*readw)(u16 *addr);
void (*writeb)(u8 value, u8 *addr);
u8 (*readb)(u8 *addr);
+ /* Disable msi if supported, PCI only */
+ int (*disable_msi_reset_irq)(struct azx *);
};
struct azx_pcm {