ARM: sun8i: Move A23 AHB1 gates out of common DTSI
authorMaxime Ripard <maxime.ripard@free-electrons.com>
Tue, 18 Aug 2015 17:34:06 +0000 (19:34 +0200)
committerMaxime Ripard <maxime.ripard@free-electrons.com>
Sun, 27 Sep 2015 08:21:31 +0000 (10:21 +0200)
The AHB1 gates were assumed to be identical between the A23 and the A33,
which turned out to be wrong. Move the A23 gates definition to the A23
DTSI.

Reported-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
arch/arm/boot/dts/sun8i-a23-a33.dtsi
arch/arm/boot/dts/sun8i-a23.dtsi

index 8f4db82084c5e7a6ab15b63a45a8d4a82886e074..04bccad977eefcff2b7af355eafdfd2449dee34e 100644 (file)
                        clock-output-names = "apb1";
                };
 
-               ahb1_gates: clk@01c20060 {
-                       #clock-cells = <1>;
-                       compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
-                       reg = <0x01c20060 0x8>;
-                       clocks = <&ahb1>;
-                       clock-indices = <1>, <6>,
-                                       <8>, <9>, <10>,
-                                       <13>, <14>,
-                                       <19>, <20>,
-                                       <21>, <24>, <26>,
-                                       <29>, <32>, <36>,
-                                       <40>, <44>, <46>,
-                                       <52>, <54>,
-                                       <57>;
-                       clock-output-names = "ahb1_mipidsi", "ahb1_dma",
-                                       "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
-                                       "ahb1_nand", "ahb1_sdram",
-                                       "ahb1_hstimer", "ahb1_spi0",
-                                       "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
-                                       "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
-                                       "ahb1_csi", "ahb1_be",  "ahb1_fe",
-                                       "ahb1_gpu", "ahb1_spinlock",
-                                       "ahb1_drc";
-               };
-
                apb1_gates: clk@01c20068 {
                        #clock-cells = <1>;
                        compatible = "allwinner,sun8i-a23-apb1-gates-clk";
index 2cc27c7a59dc389b7cf835fcaa9d7c23fd073291..4a85e213843b83f2889737d94814720ffa9a585c 100644 (file)
        };
 
        clocks {
+               ahb1_gates: clk@01c20060 {
+                       #clock-cells = <1>;
+                       compatible = "allwinner,sun8i-a23-ahb1-gates-clk";
+                       reg = <0x01c20060 0x8>;
+                       clocks = <&ahb1>;
+                       clock-indices = <1>, <6>,
+                                       <8>, <9>, <10>,
+                                       <13>, <14>,
+                                       <19>, <20>,
+                                       <21>, <24>, <26>,
+                                       <29>, <32>, <36>,
+                                       <40>, <44>, <46>,
+                                       <52>, <54>,
+                                       <57>;
+                       clock-output-names = "ahb1_mipidsi", "ahb1_dma",
+                                       "ahb1_mmc0", "ahb1_mmc1", "ahb1_mmc2",
+                                       "ahb1_nand", "ahb1_sdram",
+                                       "ahb1_hstimer", "ahb1_spi0",
+                                       "ahb1_spi1", "ahb1_otg", "ahb1_ehci",
+                                       "ahb1_ohci", "ahb1_ve", "ahb1_lcd",
+                                       "ahb1_csi", "ahb1_be",  "ahb1_fe",
+                                       "ahb1_gpu", "ahb1_spinlock",
+                                       "ahb1_drc";
+               };
+
                mbus_clk: clk@01c2015c {
                        #clock-cells = <0>;
                        compatible = "allwinner,sun8i-a23-mbus-clk";