MIPS: uasm: Add mfhi uasm instruction

It will be used later on by bpf-jit

[ralf@linux-mips.org: Resolved conflict.]

Signed-off-by: Markos Chandras <markos.chandras@imgtec.com>
Cc: linux-mips@linux-mips.org
Cc: Markos Chandras <markos.chandras@imgtec.com>
Patchwork: http://patchwork.linux-mips.org/patch/6728/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>

diff --git a/arch/mips/include/asm/uasm.h b/arch/mips/include/asm/uasm.h
index 676c12370bab3070aac913cf12b82b0e056adfe6..38312d8cde57f1b135421210a30fd66ef091ea0d 100644 (file)
--- a/arch/mips/include/asm/uasm.h
+++ b/arch/mips/include/asm/uasm.h
@@ -131,6 +131,7 @@ Ip_u1s2(_lui);
 Ip_u2s3u1(_lw);
 Ip_u3u1u2(_lwx);
 Ip_u1u2u3(_mfc0);
+Ip_u1(_mfhi);
 Ip_u1u2u3(_mtc0);
 Ip_u3u1u2(_or);
 Ip_u2u1u3(_ori);

diff --git a/arch/mips/include/uapi/asm/inst.h b/arch/mips/include/uapi/asm/inst.h
index a4bef362d7a8c5d9a1b8bdea095f7867f5b2484b..a7f6a16fd26cef3afe837739bc859257ceac8e5a 100644 (file)
--- a/arch/mips/include/uapi/asm/inst.h
+++ b/arch/mips/include/uapi/asm/inst.h
@@ -300,6 +300,7 @@ enum mm_32axf_minor_op {
        mm_mfc0_op = 0x003,
        mm_mtc0_op = 0x00b,
        mm_tlbp_op = 0x00d,
+       mm_mfhi32_op = 0x035,
        mm_jalr_op = 0x03c,
        mm_tlbr_op = 0x04d,
        mm_jalrhb_op = 0x07c,

diff --git a/arch/mips/mm/uasm-micromips.c b/arch/mips/mm/uasm-micromips.c
index aefe7441e620ab955d5cf054cb4674d10f30f2ed..c04c9c95c3c72b3d6f063ad1675509dba0c38b24 100644 (file)
--- a/arch/mips/mm/uasm-micromips.c
+++ b/arch/mips/mm/uasm-micromips.c
@@ -86,6 +86,7 @@ static struct insn insn_table_MM[] = {
        { insn_lui, M(mm_pool32i_op, mm_lui_op, 0, 0, 0, 0), RS | SIMM },
        { insn_lw, M(mm_lw32_op, 0, 0, 0, 0, 0), RT | RS | SIMM },
        { insn_mfc0, M(mm_pool32a_op, 0, 0, 0, mm_mfc0_op, mm_pool32axf_op), RT | RS | RD },
+       { insn_mfhi, M(mm_pool32a_op, 0, 0, 0, mm_mfhi32_op, mm_pool32axf_op), RS },
        { insn_mtc0, M(mm_pool32a_op, 0, 0, 0, mm_mtc0_op, mm_pool32axf_op), RT | RS | RD },
        { insn_or, M(mm_pool32a_op, 0, 0, 0, 0, mm_or32_op), RT | RS | RD },
        { insn_ori, M(mm_ori32_op, 0, 0, 0, 0, 0), RT | RS | UIMM },

diff --git a/arch/mips/mm/uasm-mips.c b/arch/mips/mm/uasm-mips.c
index 6f51543dceac274476e5b5d9ca2e225bf12ae0e6..07184927b733362b81fc47a80301c372aa980bdf 100644 (file)
--- a/arch/mips/mm/uasm-mips.c
+++ b/arch/mips/mm/uasm-mips.c
@@ -94,6 +94,7 @@ static struct insn insn_table[] = {
        { insn_lw,  M(lw_op, 0, 0, 0, 0, 0),  RS | RT | SIMM },
        { insn_lwx, M(spec3_op, 0, 0, 0, lwx_op, lx_op), RS | RT | RD },
        { insn_mfc0,  M(cop0_op, mfc_op, 0, 0, 0, 0),  RT | RD | SET},
+       { insn_mfhi,  M(spec_op, 0, 0, 0, 0, mfhi_op), RD },
        { insn_mtc0,  M(cop0_op, mtc_op, 0, 0, 0, 0),  RT | RD | SET},
        { insn_ori,  M(ori_op, 0, 0, 0, 0, 0),  RS | RT | UIMM },
        { insn_or,  M(spec_op, 0, 0, 0, 0, or_op),  RS | RT | RD },

diff --git a/arch/mips/mm/uasm.c b/arch/mips/mm/uasm.c
index 31873cdd8021b1f660a589c6a74677f0120f2c2c..29fc432788019064395a8b7779399df3d1eefe7f 100644 (file)
--- a/arch/mips/mm/uasm.c
+++ b/arch/mips/mm/uasm.c
@@ -51,10 +51,11 @@ enum opcode {
        insn_dsll32, insn_dsra, insn_dsrl, insn_dsrl32, insn_dsubu, insn_eret,
        insn_ext, insn_ins, insn_j, insn_jal, insn_jalr, insn_jr, insn_ld,
        insn_ldx, insn_ll, insn_lld, insn_lui, insn_lw, insn_lwx, insn_mfc0,
-       insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe, insn_rotr, insn_sc,
-       insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra, insn_srl, insn_srlv,
-       insn_subu, insn_sw, insn_sync, insn_syscall, insn_tlbp, insn_tlbr,
-       insn_tlbwi, insn_tlbwr, insn_wait, insn_xor, insn_xori, insn_yield,
+       insn_mfhi, insn_mtc0, insn_or, insn_ori, insn_pref, insn_rfe,
+       insn_rotr, insn_sc, insn_scd, insn_sd, insn_sll, insn_sllv, insn_sra,
+       insn_srl, insn_srlv, insn_subu, insn_sw, insn_sync, insn_syscall,
+       insn_tlbp, insn_tlbr, insn_tlbwi, insn_tlbwr, insn_wait, insn_xor,
+       insn_xori, insn_yield,
 };
 
 struct insn {
@@ -273,6 +274,7 @@ I_u2s3u1(_lld)
 I_u1s2(_lui)
 I_u2s3u1(_lw)
 I_u1u2u3(_mfc0)
+I_u1(_mfhi)
 I_u1u2u3(_mtc0)
 I_u2u1u3(_ori)
 I_u3u1u2(_or)