This makes room for off-chip IRQ controllers.
Signed-off-by: Michael Hennerich <michael.hennerich@analog.com>
Signed-off-by: Mike Frysinger <vapier@gentoo.org>
#include <linux/irqflags.h>
+/* IRQs that may be used by external irq_chip controllers */
+#define NR_SPARE_IRQS 32
+
#include <mach/anomaly.h>
/* SYS_IRQS and NR_IRQS are defined in <mach-bf5xx/irq.h> */
#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_IRQS (IRQ_PH15 + 1)
+#define NR_MACH_IRQS (IRQ_PH15 + 1)
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8
#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_IRQS (IRQ_PH15+1)
+#define NR_MACH_IRQS (IRQ_PH15 + 1)
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8
#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_IRQS (IRQ_PF15+1)
+#define NR_MACH_IRQS (IRQ_PF15 + 1)
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8
#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_IRQS (IRQ_PH15+1)
+#define NR_MACH_IRQS (IRQ_PH15 + 1)
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8
#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_IRQS (IRQ_PF15+1)
+#define NR_MACH_IRQS (IRQ_PF15 + 1)
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8
#define GPIO_IRQ_BASE IRQ_PA0
-#define NR_IRQS (IRQ_PJ15+1)
+#define NR_MACH_IRQS (IRQ_PJ15 + 1)
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
/* For compatibility reasons with existing code */
#define GPIO_IRQ_BASE IRQ_PF0
-#define NR_IRQS (IRQ_PF47 + 1)
+#define NR_MACH_IRQS (IRQ_PF47 + 1)
+#define NR_IRQS (NR_MACH_IRQS + NR_SPARE_IRQS)
#define IVG7 7
#define IVG8 8
#endif
/* if configured as edge, then will be changed to do_edge_IRQ */
- for (irq = GPIO_IRQ_BASE; irq < NR_IRQS; irq++)
+ for (irq = GPIO_IRQ_BASE; irq < NR_MACH_IRQS; irq++)
set_irq_chip_and_handler(irq, &bfin_gpio_irqchip,
handle_level_irq);