drm: Bring PLL limits in sync with DDX values.
authorKristian Høgsberg <krh@bitplanet.net>
Sat, 14 Feb 2009 01:56:50 +0000 (20:56 -0500)
committerDave Airlie <airlied@redhat.com>
Fri, 20 Feb 2009 02:21:13 +0000 (12:21 +1000)
Signed-off-by: Kristian Høgsberg <krh@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
drivers/gpu/drm/i915/intel_display.c

index 94c7c098c4ff0e418621f1b9329f3d7304dfaaa9..4f54ac55f3265d8ed3cabc645f5c17e896d2b098 100644 (file)
@@ -90,12 +90,12 @@ typedef struct {
 #define I9XX_DOT_MAX            400000
 #define I9XX_VCO_MIN           1400000
 #define I9XX_VCO_MAX           2800000
-#define I9XX_N_MIN                   3
-#define I9XX_N_MAX                   8
+#define I9XX_N_MIN                   1
+#define I9XX_N_MAX                   6
 #define I9XX_M_MIN                  70
 #define I9XX_M_MAX                 120
 #define I9XX_M1_MIN                 10
-#define I9XX_M1_MAX                 20
+#define I9XX_M1_MAX                 22
 #define I9XX_M2_MIN                  5
 #define I9XX_M2_MAX                  9
 #define I9XX_P_SDVO_DAC_MIN          5