#define S3C64XX_GPH7_ADDR_CF1 (0x06 << 28)
#define S3C64XX_GPH7_EINT_G6_7 (0x07 << 28)
-#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 32)
-#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 32)
-#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 32)
-#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 32)
-#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 32)
-
-#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 36)
-#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 36)
-#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 36)
-#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 36)
+#define S3C64XX_GPH8_MMC1_DATA6 (0x02 << 0)
+#define S3C64XX_GPH8_MMC2_DATA2 (0x03 << 0)
+#define S3C64XX_GPH8_I2S_V40_LRCLK (0x05 << 0)
+#define S3C64XX_GPH8_ADDR_CF2 (0x06 << 0)
+#define S3C64XX_GPH8_EINT_G6_8 (0x07 << 0)
+#define S3C64XX_GPH9_OUTPUT (0x01 << 4)
+#define S3C64XX_GPH9_MMC1_DATA7 (0x02 << 4)
+#define S3C64XX_GPH9_MMC2_DATA3 (0x03 << 4)
+#define S3C64XX_GPH9_I2S_V40_DI (0x05 << 4)
+#define S3C64XX_GPH9_EINT_G6_9 (0x07 << 4)