drm/i915/gen9: Correct max save/restore register count during gpu reset with GuC

In GuC submission mode, driver has to provide a list of registers to be
save/restored during gpu reset, make the max no. of registers value consistent
with that of the value defined in FW. If they are not in sync then register
save/restore during gpu reset won't work as expected.

Cc: Alex Dai <yu.dai@intel.com>
Cc: Dave Gordon <david.s.gordon@intel.com>
Signed-off-by: Arun Siluvery <arun.siluvery@linux.intel.com>
Link: http://patchwork.freedesktop.org/patch/msgid/1453132776-22229-1-git-send-email-arun.siluvery@linux.intel.com
Reviewed-by: Alex Dai <yu.dai@intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>

diff --git a/drivers/gpu/drm/i915/intel_guc_fwif.h b/drivers/gpu/drm/i915/intel_guc_fwif.h
index b4632f0bf7b2b6c383bfbd9064a1214d1d20aa20..1856a4740b839f3a78bf2902c8a07d85203f0f25 100644 (file)
--- a/drivers/gpu/drm/i915/intel_guc_fwif.h
+++ b/drivers/gpu/drm/i915/intel_guc_fwif.h
@@ -370,7 +370,7 @@ struct guc_policies {
 #define GUC_REGSET_SAVE_DEFAULT_VALUE  0x8
 #define GUC_REGSET_SAVE_CURRENT_VALUE  0x10
 
-#define GUC_REGSET_MAX_REGISTERS       20
+#define GUC_REGSET_MAX_REGISTERS       25
 #define GUC_MMIO_WHITE_LIST_START      0x24d0
 #define GUC_MMIO_WHITE_LIST_MAX                12
 #define GUC_S3_SAVE_SPACE_PAGES                10